llvm-svn: 157805

Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though.

llvm-svn: 157804

llvm-svn: 157802

llvm-svn: 157801

llvm-svn: 157799

llvm-svn: 157783

Patch by Yiannis Tsiouris!

llvm-svn: 157757

This patch will optimize the following
        movq    %rdi, %rax
        subq    %rsi, %rax
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax
to
        cmpq    %rsi, %rdi
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023
llvm-svn: 157755

It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

llvm-svn: 157745

I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.

llvm-svn: 157737

llvm-svn: 157731

it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly.  Just optimize 3 more.

llvm-svn: 157699

integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.

llvm-svn: 157698

llvm-svn: 157685

Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.

This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634

to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479

llvm-svn: 157446

llvm-svn: 157374

llvm-svn: 157358

llvm-svn: 157313

llvm-svn: 157309

Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug introduced in r157043. Fixes PR12908.

llvm-svn: 157236

Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces.

llvm-svn: 157175

It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165

llvm-svn: 157129

llvm-svn: 157127

llvm-svn: 157122

llvm-svn: 157109

Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062

llvm-svn: 157044

llvm-svn: 157043

llvm-svn: 156896

Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828

llvm-svn: 156774

llvm-svn: 156633

llvm-svn: 156615

This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

llvm-svn: 156611

but it generates int3 on x86 instead of ud2.

llvm-svn: 156593

llvm-svn: 156579

llvm-svn: 156541