llvm-svn: 140294

llvm-svn: 140292

llvm-svn: 140291

Turns out that Thumb2 ADR doesn't need special printing like LDR does.  Fix other test failures I caused.

llvm-svn: 140284

Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.

llvm-svn: 140283

Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.

llvm-svn: 140276

patch contributed by Jia Liu!

llvm-svn: 140273

These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.

llvm-svn: 140267

MipsArchVersion needs to be initialized to Mips32.

llvm-svn: 140261

llvm-svn: 140258

should be initialized to UnknownABI.

llvm-svn: 140254

Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.

llvm-svn: 140246

  assert(!"error message");

To:

  assert(0 && "error message");

which is more consistant across the code base.

llvm-svn: 140234

llvm-svn: 140233

Check if architecture & ABI combination is valid.

llvm-svn: 140230

llvm-svn: 140229

This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228

llvm-svn: 140227

In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.

llvm-svn: 140217

llvm-svn: 140214

llvm-svn: 140203

llvm-svn: 140199

llvm-svn: 140186

This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

llvm-svn: 140184

llvm-svn: 140183

Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.

llvm-svn: 140181

llvm-svn: 140178

No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160

llvm-svn: 140140

Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134

llvm-svn: 140133

llvm-svn: 140125

llvm-svn: 140119

llvm-svn: 140116

llvm-svn: 140111

llvm-svn: 140108

llvm-svn: 140106

llvm-svn: 140105

llvm-svn: 140104

llvm-svn: 140102