With this change, all supported tests in test/ExecutionEngine pass in sparcv9.

llvm-svn: 199977

These all use the compare-and-swap CASA/CASXA instructions.

llvm-svn: 199975

Add test cases to check parsing of v9 double registers and their aliased quad registers.

llvm-svn: 199974

code this looks correct, but could use review. The previous
was definitely not correct.

llvm-svn: 199940

llvm-svn: 199786

llvm-svn: 199781

Fixes PR#18521

llvm-svn: 199775

promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).

Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.

llvm-svn: 199252

This will allow it to be called from target independent parts of the main
streamer that don't know if there is a registered target streamer or not. This
in turn will allow targets to perform extra actions at specified points in the
interface: add extra flags for some labels, extra work during finalization, etc.

llvm-svn: 199174

Targets like SPARC and MIPS have delay slots and normally bundle the
delay slot instruction with the corresponding terminator.

Teach isBlockOnlyReachableByFallthrough to find any MBB operands on
bundled terminators so SPARC doesn't need to specialize this function.

llvm-svn: 199061

llvm-svn: 199033

llvm-svn: 199031

This is different from the argument passing convention which puts the
first float argument in %f1.

With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...

Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.

llvm-svn: 199028

llvm-svn: 199024

[Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.

llvm-svn: 199014

[Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated.

llvm-svn: 198910

[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.

llvm-svn: 198909

llvm-svn: 198893

llvm-svn: 198740

llvm-svn: 198739

llvm-svn: 198738

This makes it available to tools that don't link with target (like llvm-ar).

llvm-svn: 198708

subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685

Also, correct the offsets for FixupsKindInfo.

llvm-svn: 198681

llvm-svn: 198658

llvm-svn: 198592

llvm-svn: 198591

llvm-svn: 198585

llvm-svn: 198580

This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.

llvm-svn: 198579

llvm-svn: 198567

llvm-svn: 198533

__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.

llvm-svn: 198531

llvm-svn: 198484

Fixes PR18356.

llvm-svn: 198480

Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.

This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.

With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.

llvm-svn: 198438

llvm-svn: 198286

llvm-svn: 198281

[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.

llvm-svn: 198280

[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
 This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157