functionality change, just code cleanup.

llvm-svn: 25230

pointer in the epilog, not a load.

llvm-svn: 25229

Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222

pointer.  This allows us to emit stuff like this:

        li r10, 0
        stw r10, 56(r1)
        or r3, r10, r10
        or r4, r10, r10
        or r5, r10, r10
        or r6, r10, r10
        or r7, r10, r10
        or r8, r10, r10
        or r9, r10, r10
        bl L_bar$stub

instead of this:

        or r2, r1, r1     ;; Extraneous copy.
        li r10, 0
        stw r10, 56(r2)
        or r3, r10, r10
        or r4, r10, r10
        or r5, r10, r10
        or r6, r10, r10
        or r7, r10, r10
        or r8, r10, r10
        or r9, r10, r10
        bl L_bar$stub

wowness.

llvm-svn: 25221

Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.

llvm-svn: 25217

llvm-svn: 25167

llvm-svn: 25166

llvm-svn: 25164

hasInFlag, hasOutFlag.

llvm-svn: 25155

llvm-svn: 25141

Prolangs-C++/family and Prolangs-C++/primes.

llvm-svn: 25119

The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.

llvm-svn: 25114

llvm-svn: 25105

inserted in the code.

llvm-svn: 25104

pass manager do it's thing."  Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.

llvm-svn: 25100

llvm-svn: 25096

llvm-svn: 25093

llvm-svn: 25046

llvm-svn: 25045

Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017

constant offsets from statics into the address arithmetic.

llvm-svn: 24999

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997

llvm-svn: 24978

llvm-svn: 24974

llvm-svn: 24965

llvm-svn: 24964

llvm-svn: 24956

llvm-svn: 24935

llvm-svn: 24884

llvm-svn: 24874

us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register.  This also requires some asm printer work
to satisfy the darwin assembler.

For
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

We now produce:
_foo:
        lvx v0, 0, r3
        vaddfp v0, v0, v0
        stvx v0, 0, r3
        blr

Instead of:
_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24872

llvm-svn: 24871

llvm-svn: 24834

llvm-svn: 24748

llvm-svn: 24747

so that tablegen can infer all types.

llvm-svn: 24746

should work in all permutations.

llvm-svn: 24728

llvm-svn: 24720

from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24719

llvm-svn: 24716