llvm-svn: 101085

If we have this situation:

    jCC  L1
    jmp  L2
L1:
  ...
L2:
  ...

We can get a small performance boost by emitting this instead:

    jnCC L2
L1:
  ...
L2:
  ...

This testcase shows an example of this:

float func(float x, float y) {
    double product = (double)x * y;
    if (product == 0.0)
        return product;
    return product - 1.0;
}

llvm-svn: 101075

merge XCore's section into MCSectionELF

llvm-svn: 100812

api and update clients to use MCContext instead.

llvm-svn: 100808

llvm-svn: 100751

Fixes PR3440.

llvm-svn: 100736

llvm-svn: 100709

argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694

DBG_VALUE does not generate code.

llvm-svn: 100681

llvm-svn: 100599

into AsmPrinter.  Target-dependent form is still generated
by FastISel and still handled in X86 code.

llvm-svn: 100596

solution.  The only reason these don't fire with gcc-4.2 is that gcc turns off
part of -Wsign-compare in C++ on accident.

llvm-svn: 100581

llvm-svn: 100578

There is probably a more elegant way to do this.

llvm-svn: 100573

When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.

For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.

llvm-svn: 100559

This fixes the Bullet regression on i386/nocona.

llvm-svn: 100553

Operand 2 on a load instruction does not have to be a RegisterSDNode for this to
work.

llvm-svn: 100497

llvm-svn: 100480

llvm-svn: 100466

llvm-svn: 100416

llvm-svn: 100415

When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384

llvm-svn: 100381

llvm-svn: 100377

llvm-svn: 100376

which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.

Yay for reduction in magic.

llvm-svn: 100367

Restrict bit mask operations to the DomainValue class. Rename methods for
clarity.

llvm-svn: 100353

llvm-svn: 100342

llvm-svn: 100332

"asm printering" happens through MCStreamer.  This also 
Streamerizes PIC16 debug info, which escaped my attention.

This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.

llvm-svn: 100327

streamerized for everything.

llvm-svn: 100316

llvm-svn: 100315

which will abort in .o file writing mode.

llvm-svn: 100314

raw_ostream to print to.

llvm-svn: 100313

llvm-svn: 100312

llvm-svn: 100311

raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.

llvm-svn: 100307

member of AsmPrinter.  Instead, pass it in explicitly.

llvm-svn: 100306

Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304

of printOffset to pass in a stream to print to.

llvm-svn: 100296