llvm-svn: 33748

llvm-svn: 33747

llvm-svn: 33746

llvm-svn: 33745

to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744

llvm-svn: 33743

llvm-svn: 33742

llvm-svn: 33741

llvm-svn: 33740

there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739

llvm-svn: 33738

without exiting program.

llvm-svn: 33737

llvm-svn: 33736

llvm-svn: 33735

two bytes padding.

llvm-svn: 33734

llvm-svn: 33733

llvm-svn: 33732

llvm-svn: 33731

llvm-svn: 33730

llvm-svn: 33729

instructions away, i.e. its address is equal to PC.
        %r0 = tLDRpci <cp#0>
        bx
        CONSTPOOL_ENTRY 0 <cp#0>, 4

llvm-svn: 33728

llvm-svn: 33727

GEP constructors.

llvm-svn: 33726

llvm-svn: 33725

llvm-svn: 33724

llvm-svn: 33723

change preferred alignment of short, byte, bool to 4.

llvm-svn: 33722

llvm-svn: 33721

llvm-svn: 33720

llvm-svn: 33719

llvm-svn: 33718

llvm-svn: 33717

llvm-svn: 33716

llvm-svn: 33715

llvm-svn: 33714

llvm-svn: 33713

llvm-svn: 33712

instruction field, adjust it for PC value (4 for thumb, 8 for arm).

llvm-svn: 33711

llvm-svn: 33710

llvm-svn: 33709