%S5<def> = COPY %S0<kill>
First clear def map of Q1, etc.

No small test case available.

llvm-svn: 151574

After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

llvm-svn: 151531

uses of the vreg, since the old kills may no longer be valid.  This was causing
-verify-machineinstrs to complain about uses after kills, and could potentially
have been causing subtle register allocation issues, but I haven't come across a
test case yet.

llvm-svn: 151425

llvm-svn: 151417

llvm-svn: 151396

This will limit all register classes to N registers in order to stress
test register allocation.

llvm-svn: 151379

This is necessary to support the existing ppc lowering code for indirect calls.
Fixes PR12071.

llvm-svn: 151373

llvm-svn: 151364

llvm-svn: 151355

llvm-svn: 151348

Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics

llvm-svn: 151342

variable declaration as an argument because we want that address
anyhow for our debug information.

This seems to fix rdar://9965111, at least we have more debug
information than before and from reading the assembly it appears
to be the correct location.

llvm-svn: 151335

llvm-svn: 151334

asm.
<rdar://problem/10106006>

llvm-svn: 151303

llvm-svn: 151274

Rename it to LiveRegs to make it more clear what's stored inside.

llvm-svn: 151273

Assuming that a single std::set node adds 3 control words, a bitvector
can store (3*8+4)*8=224 registers in the allocated memory of a single
element in the std::set (x86_64). Also we don't have to call malloc
for every register added.

llvm-svn: 151269

Before register allocation, instructions can be moved across calls in
order to reduce register pressure.  After register allocation, we don't
gain a lot by moving callee-saved defs across calls.  In fact, since the
scheduler doesn't have a good idea how registers are used in the callee,
it can't really make good scheduling decisions.

This changes the schedule in two ways: 1. Latencies to call uses and
defs are no longer accounted for, causing some random shuffling around
calls.  This isn't really a problem since those uses and defs are
inaccurate proxies for what happens inside the callee.  They don't
represent registers used by the call instruction itself.

2. Instructions are no longer moved across calls.  This didn't happen
very often, and the scheduling decision was made on dubious information
anyway.

As with any scheduling change, benchmark numbers shift around a bit,
but there is no positive or negative trend from this change.

This makes the post-ra scheduler 5% faster for ARM targets.

The secret motivation for this patch is the introduction of register
mask operands representing call clobbers.  The most efficient way of
handling regmasks in ScheduleDAGInstrs is to model them as barriers for
physreg live ranges, but not for virtreg live ranges.  That's fine
pre-ra, but post-ra it would have the same effect as this patch.

llvm-svn: 151265

llvm-svn: 151252

of instantiated C++ templates.

Patch by Kristof Beyls!

llvm-svn: 151250

llvm-svn: 151235

llvm-svn: 151234

Ignore undef uses completely.
Use a more explicit SlotIndex API.
Add more explicit comments.

llvm-svn: 151233

Added array subscript to SparseSet for convenience.
Slight reorg to make it easier to manage the def/use sets.

llvm-svn: 151228

llvm-svn: 151226

llvm-svn: 151223

The bulk masking operations from register mask operands don't account
for reserved registers.

llvm-svn: 151222

llvm-svn: 151211

llvm-svn: 151210

llvm-svn: 151205

The standard function epilog includes a .size directive, but ppc64 uses
an alternate local symbol to tag the actual start of each function.

Until recently, binutils accepted the .size directive as:
 .size	test1, .Ltmp0-test1
however, using this directive with recent binutils will result in the error:
 .size expression for XXX does not evaluate to a constant
so we must use the label which actually tags the start of the function.

llvm-svn: 151200

Patch by Joe Groff!

llvm-svn: 151183

llvm-svn: 151178

llvm-svn: 151169

llvm-svn: 151167

Worth another 45k (1%) off of a large C++ testcase.

rdar://10909458

llvm-svn: 151144

llvm-svn: 151143

llvm-svn: 151142

The vast majority of virtual register definitions don't need an entry
in the DAG builder's VRegDefs set.

llvm-svn: 151136

Affect on SD scheduling and postRA scheduling:
Printing the DAG will display the nodes in top-down topological order.
This matches the order within the MBB and makes my life much easier in general.

Affect on misched:
We don't need to track virtual register uses at all. This is awesome.
I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A.

llvm-svn: 151135