llvm-svn: 117206

llvm-svn: 117197

llvm-svn: 117196

llvm-svn: 117195

llvm-svn: 117111

llvm-svn: 116899

llvm-svn: 116682

llvm-svn: 116588

and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432

llvm-svn: 116421

operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

llvm-svn: 116353

llvm-svn: 116282

llvm-svn: 116243

map one-to-one with the CodeGenInstruction operand number.

llvm-svn: 116238

llvm-svn: 116215

try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).

llvm-svn: 116211

llvm-svn: 116069

llvm-svn: 116068

llvm-svn: 116030

llvm-svn: 116018

llvm-svn: 115994

llvm-svn: 115986

llvm-svn: 115973

llvm-svn: 115923

llvm-svn: 115890

llvm-svn: 115884

llvm-svn: 115841

as the operator of the dag.  Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).

Unfortunately, this runs afoul of an idiom being used by llvmc.  It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo.  With this change, this is parsed as a [1,2,3] 
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.

llvm-svn: 115742

llvm-svn: 115739

where !cast is just as short.

llvm-svn: 115722

!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719

tried (but failed) to artificially constrain it to working with #NAME#.
Just allow any # in identifiers, and update the comments.

llvm-svn: 115704

simplify the X86 CMOVmr's.

llvm-svn: 115702

llvm-svn: 115664

llvm-svn: 115624

llvm-svn: 115616

instruction forms.  Now the ENTER instruction
disassembles correctly.

llvm-svn: 115573

llvm-svn: 115348

The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243

or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.

llvm-svn: 115126