1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135

latencies) of loads.

llvm-svn: 118134

llvm-svn: 118133

llvm-svn: 118131

llvm-svn: 118130

llvm-svn: 118128

llvm-svn: 118127

llvm-svn: 118126

instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125

llvm-svn: 118124

llvm-svn: 118122

llvm-svn: 118121

llvm-svn: 118120

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

clang are using.

llvm-svn: 118118

threshold given to createFunctionInliningPass().

Both opt -O3 and clang would silently ignore the -inline-threshold option.

llvm-svn: 118117

limits on their own.

llvm-svn: 118113

that have complicated tying going on.

llvm-svn: 118112

llvm-svn: 118110

llvm-svn: 118107

llvm-svn: 118106

llvm-svn: 118105

filling them in one at a time.  Previously this iterated over the
asmoperands, which left the problem of "holes".  The new approach
simplifies things.

llvm-svn: 118104

llvm-svn: 118103

llvm-svn: 118102

llvm-svn: 118099

is handled with the MC encoder.

llvm-svn: 118098

Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.

llvm-svn: 118097

llvm-svn: 118096

with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094

llvm-svn: 118093

llvm-svn: 118092

Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.

llvm-svn: 118089

llvm-svn: 118088

llvm-svn: 118087

llvm-svn: 118086

llvm-svn: 118084

in the generated .inc files.

llvm-svn: 118083

llvm-svn: 118082

    // FIXME: We should compute this sooner, we don't want to recurse here, and
    // we would like to be more functional.

In MCAssembler::ComputeFragmentSize.

llvm-svn: 118080