we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882

Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
  defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
  before any of its sub-registers. When the sub-register graph is not a
  tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
  number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

llvm-svn: 132881

functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.

llvm-svn: 132880

llvm-svn: 132876

llvm-svn: 132872

llvm-svn: 132871

memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.

llvm-svn: 132869

Patch by: Jakub Staszak!

Introduces BranchProbability. Changes unsigned to uint32_t all over and
uint64_t only when overflow is expected.

llvm-svn: 132867

Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

llvm-svn: 132865

rdar://9431466

llvm-svn: 132864

llvm-svn: 132863

default, since it usually has very few elements. This speeds up
alias queries in many cases, because AliasCache.clear() doesn't
have to visit as many buckets.

llvm-svn: 132862

<rdar://problem/9583891>

llvm-svn: 132860

llvm-svn: 132857

CallOrPrologue correctly and eliminate the existing setter.

llvm-svn: 132856

comment on their meaning.

llvm-svn: 132854

llvm-svn: 132853

llvm-svn: 132852

Thanks Bob Wilson for noticing it!

llvm-svn: 132851

Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

llvm-svn: 132849

llvm-svn: 132844

llvm-svn: 132839

llvm-svn: 132836

llvm-svn: 132834

llvm-svn: 132830

PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.

llvm-svn: 132826

and definitions when emitting global variables.  This was causing global 
declarations to be emitted as if they were definitions.
Fixes <rdar://problem/9429892>.

llvm-svn: 132825

llvm-svn: 132824

llvm-svn: 132822

llvm-svn: 132821

With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.

llvm-svn: 132816

Chris fixed this README a while back by changing how clang generates code for structs like the given struct.

llvm-svn: 132815

llvm-svn: 132814

causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811

Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine.  Part of rdar://9562809.

The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.

llvm-svn: 132809

eh edges. Swap the order of the checks to avoid it.

llvm-svn: 132806

llvm-svn: 132805

llvm-svn: 132803

VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.

llvm-svn: 132802

llvm-svn: 132800