llvm-svn: 139124

llvm-svn: 139122

InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match.

Fixes clang selfhost.

llvm-svn: 139120

exception.

llvm-svn: 139117

up do-nothing exception handling code produced by dragonegg.

llvm-svn: 139113

- Drop support for X >u 0, it's equivalent to X != 0 and should be canonicalized into the latter.
- Add X < 1 -> unlikely, which is what instcombine canonicalizes X <= 0 into.
- Add X > -1 -> likely, which is what instcombine canonicalizes X >= 0 into.

llvm-svn: 139110

Use Duncan's patch to delete the instructions in reverse order (minus the landingpad and terminator).

llvm-svn: 139090

call. The call may be in the same BB as the landingpad instruction. If that's
the case, then inserting the loads after the landingpad inst, but before the
extractvalues, causes undefined behavior.

llvm-svn: 139088

llvm-svn: 139079

values that the resume instruction uses.
PR10850

llvm-svn: 139076

the cycle of missing AVX counterparts of already present SSE* patterns

llvm-svn: 139073

llvm-svn: 139072

llvm-svn: 139071

llvm-svn: 139070

llvm-svn: 139069

duplicate it for AVX mode.

llvm-svn: 139068

llvm-svn: 139067

that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066

pattern should be matched

llvm-svn: 139065

llvm-svn: 139064

it!

llvm-svn: 139063

llvm-svn: 139062

llvm-svn: 139061

OptForSize pattern

llvm-svn: 139060

If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert.  The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users.  No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.

llvm-svn: 139059

The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057

It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056

llvm-svn: 139055

llvm-svn: 139053

Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049

llvm-svn: 139047

llvm-svn: 139044

For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040

llvm-svn: 139036

slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.

llvm-svn: 139035

case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028

llvm-svn: 139024

llvm-svn: 139023

llvm-svn: 139022

llvm-svn: 139021