llvm-svn: 30907

that it can't assume ESP is unmodified across the instrs.

llvm-svn: 30905

llvm-svn: 30891

llvm-svn: 30844

llvm-svn: 30583

operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241

llvm-svn: 30177

using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.

llvm-svn: 30156

llvm-svn: 30152

llvm-svn: 29603

llvm-svn: 29228

llvm-svn: 29194

llvm-svn: 29110

llvm-svn: 28980

llvm-svn: 28938

vector types are passed via XMM registers.

llvm-svn: 28789

llvm-svn: 28666

llvm-svn: 28606

llvm-svn: 28603

Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
  return (x << 3) + 7;
}

This can be codegen'd as:
leal 7(,%eax,8), %eax

llvm-svn: 28550

llvm-svn: 28417

- Fix a couple of minor bugs in i16immSExt8 and i16immZExt8.
- Added loadiPTR fragment used for indirect jumps and calls.

llvm-svn: 28392

llvm-svn: 28390

llvm-svn: 28371

llvm-svn: 28324

movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164

llvm-svn: 28127

that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.

llvm-svn: 28119

for now.

Patch contributed by Alexander Friedman.

llvm-svn: 27994

llvm-svn: 27948

x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

llvm-svn: 27120

failures from last night

llvm-svn: 26981

llvm-svn: 26966

V8I16, etc.

llvm-svn: 26838

llvm-svn: 26831

- Nuke a bogus comment.

llvm-svn: 26815

llvm-svn: 26604

llvm-svn: 26581