two bytes padding.

llvm-svn: 33734

llvm-svn: 33733

llvm-svn: 33729

instructions away, i.e. its address is equal to PC.
        %r0 = tLDRpci <cp#0>
        bx
        CONSTPOOL_ENTRY 0 <cp#0>, 4

llvm-svn: 33728

llvm-svn: 33727

llvm-svn: 33724

llvm-svn: 33723

change preferred alignment of short, byte, bool to 4.

llvm-svn: 33722

llvm-svn: 33721

llvm-svn: 33717

instruction field, adjust it for PC value (4 for thumb, 8 for arm).

llvm-svn: 33711

llvm-svn: 33707

llvm-svn: 33706

ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.

llvm-svn: 33703

llvm-svn: 33702

llvm-svn: 33699

- Islands are inserted right after the user MI since thumb LDR cannot encode
  negative offset.

llvm-svn: 33690

that would require > 3 instructions to materialize), load the immediate from a
constpool entry.

llvm-svn: 33667

        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664

confusion with external linkage types.

llvm-svn: 33663

llvm-svn: 33658

llvm-svn: 33657

llvm-svn: 33656

sp, imm instructions implicitly multiply the offset by 4.

llvm-svn: 33653

llvm-svn: 33652

instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651

  spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
  in thumb mode so it can be clobbered if it is properly spilled / restored
  in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
  spill by:
  push lr -> delete
  pop pc -> bx lr

llvm-svn: 33650

llvm-svn: 33649

llvm-svn: 33644

address nodes.

llvm-svn: 33636

llvm-svn: 33633

llvm-svn: 33632

1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.

NOTEs: 1. Documentation will be updated soon.
       2. llvm-upgrade should be improved to translate csret => sret.
          Before this, there will be some unexpected test fails.
llvm-svn: 33597

llvm-svn: 33569

llvm-svn: 33568

llvm-svn: 33562

Now we can compile llvm-gcc on arm-linux-gnueabi!

llvm-svn: 33558

llvm-svn: 33551

for debugging and exception handling.

llvm-svn: 33550

llvm-svn: 33549