llvm-svn: 24070

simplifies using list of records.

llvm-svn: 24069

llvm-svn: 24055

llvm-svn: 24052

llvm-svn: 24050

llvm-svn: 24015

llvm-svn: 24013

llvm-svn: 24010

llvm-svn: 24008

llvm-svn: 23983

llvm-svn: 23975

for pointing this out!

llvm-svn: 23963

definitions from the LLVM namespace, since they are all static.

llvm-svn: 23907

llvm-svn: 23894

llvm-svn: 23879

llvm-svn: 23870

active now.  Scheduling itinerary next.

llvm-svn: 23869

tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.

llvm-svn: 23854

write things like this:

def : Pat<(add GPRC:$in, 12),
          (ADD12 GPRC:$in)>;

Andrew: if this isn't enough or doesn't work for you, please lemme know.
llvm-svn: 23819

llvm-svn: 23817

instead of a happy error message

llvm-svn: 23816

def : Pat<(trunc G8RC:$in),
          (OR8To4 G8RC:$in, X0)>;

Even though this doesn't make any sense on PPC :)

llvm-svn: 23815

llvm-svn: 23814

patterns.  Certainly a logical request.

llvm-svn: 23810

llvm-svn: 23780

SelectNodeTo instead of getTargetNode when possible.

llvm-svn: 23758

a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction.  This allows FMA32
patterns to not match double expressions for example.

llvm-svn: 23748

type constraint.  This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.

llvm-svn: 23730

Overall, no functionality change yet though.

llvm-svn: 23729

llvm-svn: 23728

llvm-svn: 23725

1. If an operation has to be int or fp and the target only supports one
   int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
   for patterns involving those operators, since we do not emit the code to
   check for them yet.  This prevents PPC from generating FP ops currently.

Also move some code around into more logical places.

llvm-svn: 23724

llvm-svn: 23723

llvm-svn: 23584

llvm-svn: 23564

llvm-svn: 23562

trim down the target info structs now that we have a preferred spill register class for each callee save register

llvm-svn: 23560

llvm-svn: 23553

llvm-svn: 23550

llvm-svn: 23549