were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063

valgrind problems.

llvm-svn: 105062

llvm-svn: 105061

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 105059

Implement remaining items in neon td file.  Still need to modify emitter to generate a proper header.

llvm-svn: 105058

llvm-svn: 105014

llvm-svn: 105013

llvm-svn: 105012

(radar 8040068).

llvm-svn: 105011

llvm-svn: 105010

llvm-svn: 105009

as is done with most other cast opcode predicates.

llvm-svn: 105008

llvm-svn: 105007

llvm-svn: 105006

llvm-svn: 105005

llvm-svn: 105002

llvm-svn: 105001

align=native, at least for the platforms we support.

llvm-svn: 105000

llvm-svn: 104999

what we used to be doing, and makes sure that paired '#pragma options
align=reset' won't fail.

llvm-svn: 104998

llvm-svn: 104997

(radar 8020384)

llvm-svn: 104996

getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994

llvm-svn: 104993

llvm-svn: 104992

llvm-svn: 104991

llvm-svn: 104990

implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

llvm-svn: 104985

Currently, the backend uses the same policy, but it will soon switch to
-regalloc=fast for -O0.

llvm-svn: 104984

llvm-svn: 104982

llvm-svn: 104980

llvm-svn: 104975

llvm-svn: 104974

llvm-svn: 104970

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

rethrow inside @catch block must use objc_exception_rethrow
API. Fixes radar 8037512. Test will be added to LLVM
test suite.

llvm-svn: 104964

llvm-svn: 104963

llvm-svn: 104962

llvm-svn: 104961