Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503

llvm-svn: 53502

has exactly one MachineMemOperand, and change some X86 lowering code to
make use of it.

llvm-svn: 53498

llvm-svn: 53489

llvm-svn: 53487

instead of using the frame index for the SVOffset, which was
inconsistent.

llvm-svn: 53486

Added partial specialization of DenseMapInfo<T> for ImmutableList.

llvm-svn: 53485

Update to build_llvm. Don't output a floating point number for the version.

llvm-svn: 53484

llvm-svn: 53481

llvm-svn: 53480

use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.

llvm-svn: 53476

llvm-svn: 53474

llvm-svn: 53472

llvm-svn: 53471

llvm-svn: 53470

be no need to split the result of a vector RET node,
since they are always already legal.

llvm-svn: 53462

SINT_TO_FP libcall plus additional operations:
it might as well be a direct UINT_TO_FP libcall.
So only turn it into an SINT_TO_FP if the target
has special handling for SINT_TO_FP.

llvm-svn: 53461

llvm-svn: 53460

was presumably added after the rest of the code was
copied to LegalizeTypes.

llvm-svn: 53459

on 16 bit machines.

llvm-svn: 53458

llvm-svn: 53454

whitespace.

llvm-svn: 53453

llvm-svn: 53452

similar.

llvm-svn: 53451

llvm-svn: 53450

llvm-svn: 53449

llvm-svn: 53448

llvm-svn: 53447

the min/max values for an integer type, compare against the min/max
values we can prove contain the input.  This might be a tighter bound,
so this is general goodness.

llvm-svn: 53446

handle them in some code.

llvm-svn: 53445

was using the algorithm for folding unsigned comparisons which is
completely wrong.  This has been broken since the signless types change.

llvm-svn: 53444

This cause a regression in InstCombine/JavaCompare, which was doing the right
thing on accident.  To handle the missed case, generalize the comparisons based
on masked bits a little bit to handle comparisons against the max value. For 
example, we can now xform (slt i32 (and X, 4), 4) -> (setne i32 (and X, 4), 4)

llvm-svn: 53443

llvm-svn: 53442

llvm-svn: 53440

llvm-svn: 53438

when working on legalizetypes.  Both legalizetypes and legalizeops now
produce hte same code for CodeGen/ARM/fcopysign.ll.

llvm-svn: 53435

llvm-svn: 53434

llvm-svn: 53433

llvm-svn: 53432

llvm-svn: 53431