llvm-svn: 85571

llvm-svn: 85562

llvm-svn: 85559

llvm-svn: 85558

llvm-svn: 85556

Between scheduling regions, correctly maintain anti-dep breaking state so that we don't incorrectly rename registers that span these regions.

llvm-svn: 85537

llvm-svn: 85536

*ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp.

llvm-svn: 85530

llvm-svn: 85522

llvm-svn: 85519

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

llvm-svn: 85515

llvm-svn: 85514

indexed via the stack pointer, even if a frame pointer is present. Update the
heuristic to place it nearest the stack pointer in that case, rather than
nearest the frame pointer.

llvm-svn: 85474

the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.

llvm-svn: 85463

llvm-svn: 85460

--- Reverse-merging r85338 into '.':
U    lib/CodeGen/SimpleRegisterCoalescing.cpp
U    lib/CodeGen/SimpleRegisterCoalescing.h

llvm-svn: 85454

common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.

llvm-svn: 85441

to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec).  We need to
remove the store in this case.  Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here.  7331562.

llvm-svn: 85437

llvm-svn: 85436

I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426

llvm-svn: 85412

chains have no users, they can't be predecessors of the condition.

llvm-svn: 85394

the new instructions and leave the old one in place.

llvm-svn: 85393

recursive to avoid consuming extraordinary amounts of stack space
when processing tall graphs.

llvm-svn: 85369

otherwise unhoistable instructions in order to allow the loads
to be hoisted.

llvm-svn: 85364

llvm-svn: 85361

MachineLICM and other things which run before LiveVariables is run.

llvm-svn: 85360

if they have compatible encodings.

llvm-svn: 85359

llvm-svn: 85351

use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346

Fixed a bug in the coalescer where intervals were occasionally merged despite a real interference. This fixes rdar://problem/7157961.

llvm-svn: 85338

llvm-svn: 85325

llvm-svn: 85323

Do not held on to DenseMap slot accross map insertion. The insertion may cause the map to grow rending the slot invalid.
Use this opportunity to use ValueMap instead of DenseMap.

llvm-svn: 85298

llvm-svn: 85296

Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.

llvm-svn: 85281

(assembler,asmprinter, bc reader+writer) and document it.  Codegen
currently aborts on it.

llvm-svn: 85274

thread safe either.

llvm-svn: 85253

do anything than return "I don't know" at the moment.

llvm-svn: 85189