llvm-svn: 25103

Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997

llvm-svn: 24990

llvm-svn: 24935

* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921

llvm-svn: 24920

bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917

llvm-svn: 24900

that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899

llvm-svn: 24898

  for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888

llvm-svn: 24886

llvm-svn: 24879

llvm-svn: 24870

llvm-svn: 24781

llvm-svn: 24759

llvm-svn: 24756

* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726

leaaddr.

llvm-svn: 24724

llvm-svn: 24721

llvm-svn: 24705

llvm-svn: 24696

llvm-svn: 24690

llvm-svn: 24689

A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.

llvm-svn: 24688

llvm-svn: 24687

llvm-svn: 24686

llvm-svn: 24685

llvm-svn: 24684

llvm-svn: 24683

  This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682

llvm-svn: 24681

llvm-svn: 24675

llvm-svn: 24670

* Added X86 dec patterns.

llvm-svn: 24654

llvm-svn: 24648

llvm-svn: 24637

false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635

llvm-svn: 24611