Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890

llvm-svn: 111374

llvm-svn: 111366

The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.

llvm-svn: 111361

The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are 
expanded. This causes changes to some dejagnu tests.

llvm-svn: 111360

"SPU Application Binary Interface Specification, v1.9" by
IBM. 
Specifically: use r3-r74 to pass parameters and the return value.

llvm-svn: 111358

  gep P, (zext x) != gep P, (sext x)

DecomposeGEPExpression was getting this wrong, confusing
basicaa.

llvm-svn: 111352

from the LHS should disable reconsidering that pred on the
RHS.  However, knowing something about the pred on the RHS
shouldn't disable subsequent additions on the RHS from
happening.

llvm-svn: 111349

llvm-svn: 111348

llvm-svn: 111345

llvm-svn: 111344

llvm-svn: 111343

llvm-svn: 111342

Testcase from Nick Lewycky.

llvm-svn: 111341

llvm-svn: 111339

llvm-svn: 111337

llvm-svn: 111325

(e.g. errs()) fails in close() due to (e.g.) a broken pipe.  As
previously written, the had_error() flag would get set and then
the raw_ostream dtor would report a fatal error.  There is nothing
the client can do about this and we have no way to report the error,
so just eat it.

llvm-svn: 111321

into report_fatal_error.  Just blast the string to stderr with write(2)
and hope for the best!  Part of rdar://8318441

llvm-svn: 111320

vector heavy code.  I'll re-enable when we've tracked down the problem.

llvm-svn: 111318

where the step value is an induction variable from an outer loop, to
avoid trouble trying to re-expand such expressions. This effectively
hides such expressions from indvars and lsr, which prevents them
from getting into trouble.

llvm-svn: 111317

the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.

Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.

llvm-svn: 111315

CrashRecovery: Clear the current context on the first crash, to avoid re-entering it if the cleanup code crashes.

llvm-svn: 111309

CrashRecovery: Add CrashRecoveryContext::GetCurrent(), so clients can find the active context from anywhere.

llvm-svn: 111308

llvm-svn: 111307

PR 7882.  Follows suggestion by Amaury Pouly, thanks.

llvm-svn: 111306

llvm-svn: 111291

  - Do not clobber al during variadic calls, this is AMD64 ABI-only feature
  - Emit wincall64, where necessary
Patch by Cameron Esfahani!

llvm-svn: 111289

Patch by Cameron Esfahani!

llvm-svn: 111288

PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed.

llvm-svn: 111285

llvm-svn: 111281

llvm-svn: 111277

llvm-svn: 111274

llvm-svn: 111271

llvm-svn: 111266

Hello world builds & runs now on i386/ELF with -integrated-as.

llvm-svn: 111264

Modernize predicates a bit.

The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.

llvm-svn: 111263

whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890

llvm-svn: 111262

llvm-svn: 111260

llvm-svn: 111259

Move the decision logic whether it's a good idea to split a critical edge to clients. Also fixed an erroneous check. An edge is only a back edge when the from and to blocks are in the same loop.

llvm-svn: 111256