Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

proper function to do it.

llvm-svn: 138550

llvm-svn: 138546

llvm-svn: 138541

llvm-svn: 138539

Hook up 64-bit atomic load/store on x86-32.  I plan to write more efficient implementations eventually.

llvm-svn: 138505

.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184

llvm-svn: 138504

llvm-svn: 138502

Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494

Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488

llvm-svn: 138486

llvm-svn: 138469

llvm-svn: 138441

variable sized alloca.

llvm-svn: 138433

Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.

llvm-svn: 138427

permutations. Also tidy up some patterns and make them close to their
instruction definition!

llvm-svn: 138392

This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)

Conflicts:

	test/Transforms/InstCombine/bitcast.ll

llvm-svn: 138366

llvm-svn: 138364

llvm-svn: 138363

llvm-svn: 138362

llvm-svn: 138361

llvm-svn: 138360

llvm-svn: 138359

llvm-svn: 138354

llvm-svn: 138352

llvm-svn: 138349

llvm-svn: 138348

Not including tSTRspi.

llvm-svn: 138347

llvm-svn: 138345

llvm-svn: 138342

Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

llvm-svn: 138341

1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector

llvm-svn: 138340

Fix two more instances of mis-matched operand names breaking disassembly.  Found by randomized testing.

llvm-svn: 138337

llvm-svn: 138336

Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.

llvm-svn: 138321

SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317

llvm-svn: 138312

llvm-svn: 138311

llvm-svn: 138308

llvm-svn: 138304