- In thumb mode, a new constpool island BB size should be 4 + 2 to
  compensate for the potential padding due to alignment requirement.

llvm-svn: 33753

affected part is codegen of "memove" inside x86 backend. This fixes
PR1144

llvm-svn: 33752

to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744

llvm-svn: 33743

llvm-svn: 33741

there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739

two bytes padding.

llvm-svn: 33734

llvm-svn: 33733

llvm-svn: 33732

llvm-svn: 33729

instructions away, i.e. its address is equal to PC.
        %r0 = tLDRpci <cp#0>
        bx
        CONSTPOOL_ENTRY 0 <cp#0>, 4

llvm-svn: 33728

llvm-svn: 33727

llvm-svn: 33724

llvm-svn: 33723

change preferred alignment of short, byte, bool to 4.

llvm-svn: 33722

llvm-svn: 33721

llvm-svn: 33719

llvm-svn: 33717

instruction field, adjust it for PC value (4 for thumb, 8 for arm).

llvm-svn: 33711

llvm-svn: 33709

llvm-svn: 33707

llvm-svn: 33706

ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.

llvm-svn: 33703

llvm-svn: 33702

llvm-svn: 33699

- Islands are inserted right after the user MI since thumb LDR cannot encode
  negative offset.

llvm-svn: 33690

that would require > 3 instructions to materialize), load the immediate from a
constpool entry.

llvm-svn: 33667

        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664

confusion with external linkage types.

llvm-svn: 33663

llvm-svn: 33658

llvm-svn: 33657

llvm-svn: 33656

sp, imm instructions implicitly multiply the offset by 4.

llvm-svn: 33653

llvm-svn: 33652

instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651

  spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
  in thumb mode so it can be clobbered if it is properly spilled / restored
  in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
  spill by:
  push lr -> delete
  pop pc -> bx lr

llvm-svn: 33650

llvm-svn: 33649

llvm-svn: 33644

llvm-svn: 33639

address nodes.

llvm-svn: 33636