llvm-svn: 53308

llvm-svn: 53307

llvm-svn: 53306

llvm-svn: 53305

llvm-svn: 53304

llvm-svn: 53303

llvm-svn: 53302

llvm-svn: 53301

llvm-svn: 53300

llvm-svn: 53299

llvm-svn: 53298

llvm-svn: 53297

llvm-svn: 53296

llvm-svn: 53295

llvm-svn: 53294

llvm-svn: 53292

llvm-svn: 53291

llvm-svn: 53290

llvm-svn: 53280

llvm-svn: 53278

llvm-svn: 53277

llvm-svn: 53274

llvm-svn: 53272

llvm-svn: 53270

This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason.  I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.

llvm-svn: 53254

llvm-svn: 53237

llvm-svn: 53227

llvm-svn: 53215

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

llvm-svn: 53209

ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%.

llvm-svn: 53208

TargetRegisterDesc::Name field is the same as the abstract register name. There is no need for targets to specify register names in addition to their AsmName's.

llvm-svn: 53207

pool-allocating MachineInstrs.

llvm-svn: 53198

llvm-svn: 53196

llvm-svn: 53192

llvm-svn: 53179

llvm-svn: 53177

important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146

hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes.  No change if the
new LegalizeTypes infrastructure is not turned on.

llvm-svn: 53137

moves in order to get correct debug info.  Since
I can't imagine how any target could possibly
be any different, I've just stripped out the
option: now all the world's like Darwin!

llvm-svn: 53134