- Oct 02, 2010
-
-
Devang Patel authored
llvm-svn: 115378
-
Jim Grosbach authored
llvm-svn: 115377
-
Jim Grosbach authored
llvm-svn: 115376
-
Eric Christopher authored
llvm-svn: 115375
-
Jim Grosbach authored
llvm-svn: 115373
-
Jim Grosbach authored
llvm-svn: 115370
-
Jim Grosbach authored
'InstPrinter' to fall into line with the other MC-ized assembly printer using targets. llvm-svn: 115367
-
Evan Cheng authored
llvm-svn: 115365
-
Owen Anderson authored
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now, stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide more nuanced estimates in the future. llvm-svn: 115364
-
Jim Grosbach authored
InstPrinter) subdir llvm-svn: 115363
-
Devang Patel authored
llvm-svn: 115362
-
Jim Grosbach authored
been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. llvm-svn: 115360
-
Jim Grosbach authored
delay. Anton and PIC16 folks, if this is still good to keep, please go ahead and add it back in with an updated comment about when would be a good time to revisit. llvm-svn: 115358
-
- Oct 01, 2010
-
-
Evan Cheng authored
llvm-svn: 115354
-
Evan Cheng authored
llvm-svn: 115353
-
Bill Wendling authored
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else. llvm-svn: 115352
-
Eric Christopher authored
llvm-svn: 115350
-
Francois Pichet authored
llvm-svn: 115348
-
Evan Cheng authored
llvm-svn: 115344
-
Eric Christopher authored
llvm-svn: 115342
-
Owen Anderson authored
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2. llvm-svn: 115341
-
Owen Anderson authored
llvm-svn: 115339
-
Owen Anderson authored
Now that the profitable bits of EnableFullLoadPRE have been enabled by default, rip out the remainder. Anyone interested in more general PRE would be better served by implementing it separately, to get real anticipation calculation, etc. llvm-svn: 115337
-
Evan Cheng authored
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
-
Devang Patel authored
llvm-svn: 115326
-
Devang Patel authored
llvm-svn: 115325
-
Devang Patel authored
Fix code gen crash reported in PR 8235. We still lose debug info for the unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case. llvm-svn: 115323
-
Jim Grosbach authored
llvm-svn: 115314
-
Benjamin Kramer authored
llvm-svn: 115311
-
Gabor Greif authored
llvm-svn: 115310
-
Bill Wendling authored
llvm-svn: 115309
-
Bill Wendling authored
llvm-svn: 115308
-
Bill Wendling authored
llvm-svn: 115307
-
Kalle Raiskila authored
Also remove some code that died in the process. One now non-existant ori is checked for. llvm-svn: 115306
-
Eric Christopher authored
memcpy alignment is the minimum of the incoming alignments. Fixes PR 8266. llvm-svn: 115305
-
Bill Wendling authored
llvm-svn: 115304
-
Bill Wendling authored
llvm-svn: 115303
-
Chris Lattner authored
llvm-svn: 115300
-
Chris Lattner authored
llvm-svn: 115297
-
Chris Lattner authored
llvm-svn: 115296
-