Now this works with and without --with-clang-srcdir, with and
without an out-of-tree build.

llvm-svn: 149749

llvm-svn: 149737

llvm-svn: 149736

llvm-svn: 149732

llvm-svn: 149730

llvm-svn: 149728

They are not used any more. Simply use SlotIndex() to get an invalid
index.

llvm-svn: 149727

llvm-svn: 149724

llvm-svn: 149722

llvm-svn: 149717

llvm-svn: 149716

Calls that use register mask operands don't have implicit defs for
returned values.  The register mask operand handles the call clobber,
but it always behaves like a set of dead defs.

Add live implicit defs for any implicitly defined physregs that are
actually used.

llvm-svn: 149715

llvm-svn: 149714

When adding the {-1, -1} entry to the DFAStateInputTable, we
need to increment the index used to populate the DFAStateEntryTable.
Otherwise, the entry table will be off by one for each transition
after the {-1, -1} entry. PR11908.

llvm-svn: 149713

llvm-svn: 149712

llvm-svn: 149709

SelectionDAG has 4 different ways of passing physreg defs to users.
Collect all of the uses at the same time, and pass all of them to
MI->setPhysRegsDeadExcept() to mark the remaining defs dead.

The setPhysRegsDeadExcept() function will soon add the required
implicit-defs to instructions with register mask operands.

llvm-svn: 149708

llvm-svn: 149706

llvm-svn: 149705

llvm-svn: 149704

llvm-svn: 149698

The type-legalizer often scalarizes code. One of the common patterns is extract-and-truncate.
In this patch we optimize this pattern and convert the sequence into extract op of a narrow type.
This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases.

llvm-svn: 149692

llvm-svn: 149683

disassembler, just like the generic disassembler.

llvm-svn: 149681

Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.

llvm-svn: 149680

llvm-svn: 149678

llvm-svn: 149674

Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

llvm-svn: 149672

llvm-svn: 149671

needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668

dylib. This regressed with r145408. I will try to make a test case and add it
so that this doesn't happen again.

llvm-svn: 149667

llvm-svn: 149655

PHI nodes which were matched, rather than climbing up the
original PHI node's operands to rediscover PHI nodes for
recording, since the PHI nodes found that are not
necessarily part of the matched set.
This fixes rdar://10589171.

llvm-svn: 149654

that just uses the new toolchain probing logic. This fixes linking with -m32 on
64 bit systems (the /32 dir was not being added to the search).

llvm-svn: 149651

llvm-svn: 149650

llvm-svn: 149649

More targetted fix replacing d0e277d272d517ca1cda368267d199f0da7cad95.

llvm-svn: 149648

This reverts commit d0e277d272d517ca1cda368267d199f0da7cad95.

llvm-svn: 149647

It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646

llvm-svn: 149643