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  1. Mar 13, 2008
  2. Mar 12, 2008
    • Evan Cheng's avatar
      Experimental scheduler change to schedule / coalesce the copies added for... · 65e9d5f1
      Evan Cheng authored
      Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted:
      
      entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
      Live Ins: %EAX %EDX %ECX
              %reg1031<def> = MOVPC32r 0
              %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
              %reg1028<def> = MOV32rr %EAX
              %reg1029<def> = MOV32rr %EDX
              %reg1030<def> = MOV32rr %ECX
              %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
              %reg1025<def> = MOV32rr %reg1029
              %reg1026<def> = MOV32rr %reg1030
              %reg1024<def> = MOV32rr %reg1028
      
      The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.
      
      With -schedule-livein-copies:
      entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
      Live Ins: %EAX %EDX %ECX
              %reg1031<def> = MOVPC32r 0
              %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
              %reg1024<def> = MOV32rr %EAX
              %reg1025<def> = MOV32rr %EDX
              %reg1026<def> = MOV32rr %ECX
              %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]
      
      Much better!
      
      llvm-svn: 48307
      65e9d5f1
    • Duncan Sands's avatar
      Initial soft-float support for LegalizeTypes. I rewrote · 723849a1
      Duncan Sands authored
      the fcopysign expansion from LegalizeDAG to get rid of
      what seems to be a bug: the use of sign extension means
      that when copying the sign bit from an f32 to an f64,
      the upper 32 bits of the f64 (now an i64) are set, not
      just the top bit...  I also generalized it to work for
      any sized floating point types, and removed the bogosity:
        SDOperand Mask1 = (SrcVT == MVT::f64)
          ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
          : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
        Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
      (here SrcNVT is an integer with the same size as SrcVT).
      As far as I can see this takes a 1 << 63, converts to
      a double, converts that to a floating point constant
      then converts that to an integer constant, ending up
      with... 1 << 63 as an integer constant!  So I just
      generate this integer constant directly.
      
      llvm-svn: 48305
      723849a1
    • Dan Gohman's avatar
      Change VirtRegMap's dump to dump to cerr, not DOUT, so that it · 34ae72c4
      Dan Gohman authored
      can be called from within a debuger without having -debug specified
      on the command-line.
      
      llvm-svn: 48298
      34ae72c4
    • Dan Gohman's avatar
      Fix typos in comments. · bf68f9fd
      Dan Gohman authored
      llvm-svn: 48297
      bf68f9fd
    • Duncan Sands's avatar
      Fix typo. · c54fe97f
      Duncan Sands authored
      llvm-svn: 48295
      c54fe97f
    • Duncan Sands's avatar
      Don't try to extract an i32 from an f64. This · 87de65fc
      Duncan Sands authored
      getCopyToParts problem was noticed by the new
      LegalizeTypes infrastructure.  In order to avoid
      this kind of thing in the future I've added a
      check that EXTRACT_ELEMENT is only used with
      integers.  Once LegalizeTypes is up and running
      most likely BUILD_PAIR and EXTRACT_ELEMENT can
      be removed, in favour of using apints instead.
      
      llvm-svn: 48294
      87de65fc
    • Chris Lattner's avatar
      Reimplement the parameter attributes support, phase #1. hilights: · 8a923e7c
      Chris Lattner authored
      1. There is now a "PAListPtr" class, which is a smart pointer around
         the underlying uniqued parameter attribute list object, and manages
         its refcount.  It is now impossible to mess up the refcount.
      2. PAListPtr is now the main interface to the underlying object, and
         the underlying object is now completely opaque.
      3. Implementation details like SmallVector and FoldingSet are now no
         longer part of the interface.
      4. You can create a PAListPtr with an arbitrary sequence of
         ParamAttrsWithIndex's, no need to make a SmallVector of a specific 
         size (you can just use an array or scalar or vector if you wish).
      5. All the client code that had to check for a null pointer before
         dereferencing the pointer is simplified to just access the 
         PAListPtr directly.
      6. The interfaces for adding attrs to a list and removing them is a
         bit simpler.
      
      Phase #2 will rename some stuff (e.g. PAListPtr) and do other less 
      invasive changes.
      
      llvm-svn: 48289
      8a923e7c
    • Owen Anderson's avatar
      Improve the return slot optimization to be both more aggressive (not limited... · 6ff0b822
      Owen Anderson authored
      Improve the return slot optimization to be both more aggressive (not limited to sret parameters), and 
      safer (when the passed pointer might be invalid).  Thanks to Duncan and Chris for the idea behind this, 
      and extra thanks to Duncan for helping me work out the trap-safety.
      
      llvm-svn: 48280
      6ff0b822
    • Evan Cheng's avatar
      Clean up my own mess. · 99ee78ef
      Evan Cheng authored
      X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
      
      llvm-svn: 48279
      99ee78ef
    • Owen Anderson's avatar
    • Owen Anderson's avatar
      When we're determining what registers to coallesce, track the VNInfo IDs for the definitions that · 70aaab6d
      Owen Anderson authored
      feed the PHI instructions.  We'll need these IDs in order to update LiveIntervals properly.
      
      llvm-svn: 48277
      70aaab6d
    • Chris Lattner's avatar
    • Evan Cheng's avatar
      Total brain cramp. · 0903aef2
      Evan Cheng authored
      llvm-svn: 48274
      0903aef2
    • Chris Lattner's avatar
      This is a simple fix for getting error messages from dlerror in · 1f49988a
      Chris Lattner authored
      LoadLibraryPermanently. The current code modifies the value of a pointer
      that is passed by value, so the caller never gets the message.
      
      Patch by Julien Lerouge!
      
      llvm-svn: 48270
      1f49988a
    • Dale Johannesen's avatar
      One more bit of Altivec parameter passing. · 0d98256c
      Dale Johannesen authored
      llvm-svn: 48269
      0d98256c
    • Anton Korobeynikov's avatar
      Be backward compatible · 2f22e3f6
      Anton Korobeynikov authored
      llvm-svn: 48268
      2f22e3f6
    • Devang Patel's avatar
      Check multiple return values. · cc189b56
      Devang Patel authored
      llvm-svn: 48267
      cc189b56
    • Dale Johannesen's avatar
      Implement Altivec passing to varargs functions on ppc. · b28456ef
      Dale Johannesen authored
      llvm-svn: 48264
      b28456ef
    • Evan Cheng's avatar
      Set NextMII after issuing a physical register spill. · 105cb398
      Evan Cheng authored
      llvm-svn: 48263
      105cb398
    • Devang Patel's avatar
      Fix attribute handling. · fa8667a2
      Devang Patel authored
      llvm-svn: 48262
      fa8667a2
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