Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

Debug info intrinsics win for now.

llvm-svn: 107850

llvm-svn: 107832

llvm-svn: 107831

address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830

llvm-svn: 107826

in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825

llvm-svn: 107823

llvm-svn: 107820

llvm-svn: 107818

llvm-svn: 107811

This fixes PR7540.

llvm-svn: 107809

a separate DCE pass over MachineInstrs.

llvm-svn: 107804

a bunch of stuff, to allow the target-independent calling convention
logic to be employed.

llvm-svn: 107800

llvm-svn: 107798

around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791

instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.

llvm-svn: 107789

code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786

llvm-svn: 107752

llvm-svn: 107750

Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes

llvm-svn: 107749

llvm-svn: 107747

llvm-svn: 107746

llvm-svn: 107743

they've been tested to work.

llvm-svn: 107742

llvm-svn: 107740

than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734

allocated to consecutive registers.

llvm-svn: 107730

print the (%rip) only if the 'a' modifier is present.
PR 7528.

llvm-svn: 107727

This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725

llvm-svn: 107723

llvm-svn: 107720

llvm-svn: 107717

Update VEX encoding to support those new instructions

llvm-svn: 107715

SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712

llvm-svn: 107710

llvm-svn: 107701

the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691

llvm-svn: 107678

if profitable.

llvm-svn: 107673