llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

llvm-svn: 127003

implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.

llvm-svn: 78900

llvm-svn: 78894

options, which don't appear to be useful.  -enable-mips-absolute-call is
completely unused (and unless I'm mistaken, is supposed to have the 
same effect that -relocation-model=dynamic-no-pic should have), 
and -disable-mips-abicall appears to be effectively a 
synonym for -relocation-model=static. Adjust the few users of hasABICall
to checks which seem more appropriate.  Update MipsSubtarget, 
MipsTargetMachine, and MipselTargetMachine to synchronize with recent 
changes.

llvm-svn: 77938

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

llvm-svn: 76936

llvm-svn: 72483

http://llvm.org/bugs/show_bug.cgi?id=2751

Abicall was enabled even when static code model was provided 
in the command line.
The correct behavior is to disable abicall when static is
specified.

llvm-svn: 56228

llvm-svn: 55203

is lowered properly and covers everything LowerSELECT_CC did.
Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This
avoid the ugly instruction by instruction checking in printOperand.
Added a swap instruction present in the allegrex core.
Added two conditional instructions present in the allegrex core : MOVZ and MOVN.
They both allow a more efficient SELECT operation for integers.
Also added SELECT patterns to optimize MOVZ and MOVN usage.
The brcond and setcc patterns were cleaned: redundant and suboptimal patterns
were
removed. The suboptimals were replaced by more efficient ones.
Fixed some instructions that were using immZExt16 instead of immSExt16.

llvm-svn: 54724

llvm-svn: 54516

llvm-svn: 54514

llvm-svn: 54213

Added gp_rel relocations to support addressing small section contents.
Added command line to specify small section threshold in bytes.

llvm-svn: 53869

Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and 
-mno-shared). HasAbsoluteCall is not implemented but HasABICall is the 
default for o32 ABI. Now, both should help into a more accurate 
relocation types implementation. 
Added IsLinux is needed to choose between asm directives.
Instruction name strings cleanup.
AsmPrinter improved.

llvm-svn: 53551

llvm-svn: 53277

important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146

Added support for mips little endian arch => mipsel

llvm-svn: 51923

llvm-svn: 45418

llvm-svn: 43749

llvm-svn: 41159

- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461

llvm-svn: 33492

llvm-svn: 24013

CPU.

llvm-svn: 23974

llvm-svn: 23908

llvm-svn: 23904

compile with an assertion that the tables are not sorted!

llvm-svn: 23591

llvm-svn: 23569

llvm-svn: 23531