Update VEX encoding to support those new instructions

llvm-svn: 107715

llvm-svn: 107599

- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204

Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912

llvm-svn: 106906

Support VEX encoding for MRMDestReg

llvm-svn: 106896

- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787

llvm-svn: 106588

llvm-svn: 106365

segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364

Handle OpSize TSFlag for AVX

llvm-svn: 105869

llvm-svn: 105860

Introduce the VEX_X field

llvm-svn: 105859

that rip-relative address when executing in 32-bit mode.

llvm-svn: 105656

immediates to avoid breaking the build.

llvm-svn: 105652

In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524

yet, only assembly encoding support.

llvm-svn: 105521

llvm-svn: 98954

were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880

llvm-svn: 98855

files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839

not the end of the field, fixing rdar://7651978

llvm-svn: 96330

encoding them into nothing.

llvm-svn: 96110

llvm-svn: 96088

llvm-svn: 96076

fix swapgs to be spelled right.

llvm-svn: 96058

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

rip-relative addresses, and add a testcase.

llvm-svn: 96040

llvm-svn: 96038

addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

llvm-svn: 96031

llvm-svn: 96029

llvm-svn: 96028

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.

llvm-svn: 95929

the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.

llvm-svn: 95924