llvm-svn: 26158

llvm-svn: 26157

create these nodes with flag results.  Remember that we legalized them.

llvm-svn: 26156

llvm-svn: 26155

llvm-svn: 26154

llvm-svn: 26153

for a sign extension.

This fixes InstCombine/2006-02-13-DemandedMiscompile.ll and Ptrdist/bc.

llvm-svn: 26152

llvm-svn: 26151

llvm-svn: 26150

name' issue.

llvm-svn: 26149

llvm-svn: 26148

llvm-svn: 26147

llvm-svn: 26146

llvm-svn: 26145

following handy-dandy properties:

1. it is always correct now
2. it is much faster than before
3. it is easier to understand

This implementation builds off of the recent simplifications of the
legalizer that made it single-pass instead of iterative.

This fixes JM/lencod, JM/ldecod, and
CodeGen/Generic/2006-02-12-InsertLibcall.ll (at least on PPC).

llvm-svn: 26144

CALLSEQ_START nodes.

llvm-svn: 26143

llvm-svn: 26142

llvm-svn: 26141

llvm-svn: 26140

llvm-svn: 26139

of the input.  This fixes the mediabench/gsm/toast failure last night.

llvm-svn: 26138

llvm-svn: 26137

PowerPC/and-imm.ll

llvm-svn: 26136

llvm-svn: 26135

llvm-svn: 26134

llvm-svn: 26133

1. Teach GetConstantInType to handle boolean constants.
2. Teach instcombine to fold (compare X, CST) when X has known 0/1 bits.
   Testcase here: set.ll:test22
3. Improve the "(X >> c1) & C2 == 0" folding code to allow a noop cast
   between the shift and and.  More aggressive bitfolding for other reasons
   was turning signed shr's into unsigned shr's, leaving the noop cast in
   the way.

llvm-svn: 26131

llvm-svn: 26130

xfail marker with it

llvm-svn: 26129

llvm-svn: 26128

llvm-svn: 26127

llvm-svn: 26126

llvm-svn: 26124

llvm-svn: 26123

This allows us to simplify on conditions where bits are not known, but they
are not demanded either!  This also fixes a couple of bugs in
ComputeMaskedBits that were exposed during this work.

In the future, swaths of instcombine should be removed, as this code
subsumes a bunch of ad-hockery.

llvm-svn: 26122

llvm-svn: 26121

fix storing booleans (grawp missed this one)

llvm-svn: 26120

now short immediates will get matched (previously constants were all
triggering movl 64bit imm fat instructions)

llvm-svn: 26119

loops and their subloops.

llvm-svn: 26118

X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.

llvm-svn: 26117