llvm-svn: 117080

llvm-svn: 117076

llvm-svn: 117072

setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879

llvm-svn: 116768

llvm-svn: 116612

llvm-svn: 116604

llvm-svn: 116588

llvm-svn: 116566

llvm-svn: 116560

llvm-svn: 116537

and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534

pseudonym.

llvm-svn: 116512

llvm-svn: 116498

llvm-svn: 116488

llvm-svn: 116449

llvm-svn: 116447

llvm-svn: 116444

llvm-svn: 116440

llvm-svn: 116437

and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432

llvm-svn: 116428

wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

llvm-svn: 116427

llvm-svn: 116421

llvm-svn: 116414

llvm-svn: 116412

arithmetic-with-carry-in instructions.

llvm-svn: 116384

and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377

explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367

llvm-svn: 116321

ARM instructions.

llvm-svn: 116313

register operand.

llvm-svn: 116259

matching in tblgen to do the predicate operand.

llvm-svn: 116213

concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112

llvm-svn: 115884

llvm-svn: 115853

llvm-svn: 115845

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

llvm-svn: 115370

llvm-svn: 115193