The LSDA is a bit difficult for the non-initiated to read. Even with comments,
it's not always clear what's going on. This wraps the ASM streamer in a class
that retains the LSDA and then emits a human-readable description of what's
going on in it.

So instead of having to make sense of:

Lexception1:
        .byte   255
        .byte   155
        .byte   168
        .space  1
        .byte   3
        .byte   26
Lset0 = Ltmp7-Leh_func_begin1
      .long     Lset0
Lset1 = Ltmp812-Ltmp7
      .long     Lset1
Lset2 = Ltmp913-Leh_func_begin1
      .long     Lset2
      .byte     3
Lset3 = Ltmp812-Leh_func_begin1
      .long     Lset3
Lset4 = Leh_func_end1-Ltmp812
      .long     Lset4
      .long     0
      .byte     0
      .byte     1
      .byte     0
      .byte     2
      .byte     125
      .long     __ZTIi@GOTPCREL+4
      .long     __ZTIPKc@GOTPCREL+4

you can read this instead:

## Exception Handling Table: Lexception1
##  @LPStart Encoding: omit
##    @TType Encoding: indirect pcrel sdata4
##        @TType Base: 40 bytes
## @CallSite Encoding: udata4
## @Action Table Size: 26 bytes

## Action 1:
##   A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception.
##     For type(s):  __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4
## Action 2:
##   A throw between Ltmp812 and Leh_func_end1 does not have a landing pad.

llvm-svn: 133286

Followup to 132926.  rdar://problem/9265821

llvm-svn: 133285

llvm-svn: 133274

and other backward compatibility hacks.

llvm-svn: 133273

llvm-svn: 133272

llvm-svn: 133271

llvm-svn: 133270

llvm-svn: 133269

llvm-svn: 133268

llvm-svn: 133267

to functions and call/invokes, not to types.

llvm-svn: 133266

llvm-svn: 133265

llvm-svn: 133260

* We should change the generated code because of a debug use.
* Avoid creating debug uses of undef, as they become a kill.
Test to follow.

llvm-svn: 133255

llvm-svn: 133254

* rounding modes for fp add, mul, sub now use .rn
* float -> int rounding correctly uses .rzi not .rni
* 32bit fdiv for sm13 uses div.rn (instead of div.approx)
* 32bit fdiv for sm10 now uses div (instead of div.approx)

Approx is not IEEE 754 compatible (and should be optionally set by a flag to the backend instead). The .rn rounding modifier is the PTX default anyway, but it's better to be explicit.

All these modifiers should be available by using __fmul_rz functions for example, but support will need to be added for this in the backend.

Patch by Dan Bailey

llvm-svn: 133253

llvm-svn: 133251

Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to PBQP allocation. Patch by Arnaud Allard de Grandmaison.

llvm-svn: 133249

needed since llvm-gcc 3.4 days.

llvm-svn: 133248

remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue.

llvm-svn: 133247

was replaced with return of a "first class aggregate".

llvm-svn: 133245

llvm-svn: 133244

syntax and has been long obsolete.  As usual, updating the tests is the nasty
part of this.

llvm-svn: 133242

be made, but this is already a win.

llvm-svn: 133240

The reserved R14-R15 are always saved in the prolog, and using CSRs
starting from R13 allows them to be saved in one instruction.

Thanks to Anton for explaining this.

llvm-svn: 133233

the old malloc/free instructions, and for 'sext' and 'zext' as function 
attributes (they are spelled signext/zeroext now), and support for result
value attributes being specified after a function.

Additionally, diagnose invalid attributes on functions with an error message
instead of an abort in the verifier.

llvm-svn: 133229

tail call pseudoinstruction. This fixes <rdar://problem/9624333>.

llvm-svn: 133227

Patch by Richard Smith!

llvm-svn: 133220

Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.

The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.

llvm-svn: 133216

In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).

<rdar://problem/9624323>

llvm-svn: 133210

No functional change was intended.

llvm-svn: 133202

llvm-svn: 133197

llvm-svn: 133194

This limits the # address spaces to 2^23, which should be good enough.

llvm-svn: 133192

the SubclassData field, saving a word.

llvm-svn: 133191

llvm-svn: 133190

than trying to insert them immediately after the invoke.

llvm-svn: 133188

I think PBQP could use RegisterClassInfo, but it didn't fit neatly with
the external interfaces that PBQP uses, so I'll leave that to Lang.

llvm-svn: 133186

BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184

Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand.  This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.

llvm-svn: 133178