llvm-svn: 141001

Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.

llvm-svn: 140997

llvm-svn: 140993

Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.

llvm-svn: 140974

Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.

llvm-svn: 140971

llvm-svn: 140955

Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.

llvm-svn: 140954

to appease nightly testers.  Not quite there yet.

llvm-svn: 140953

llvm-svn: 140947

llvm-svn: 140946

llvm-svn: 140943

llvm-svn: 140942

llvm-svn: 140941

llvm-svn: 140940

llvm-svn: 140939

Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.

llvm-svn: 140938

llvm-svn: 140937

and block addresses.

llvm-svn: 140936

* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.

llvm-svn: 140935

llvm-svn: 140934

pool value.

It's not used right now, but will be soon.

llvm-svn: 140933

useful if an optimization assumes the stack has been realigned.  Credit to
Eli for his assistance.
rdar://10043857

llvm-svn: 140924

This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898

It will soon need the context.

llvm-svn: 140896

llvm-svn: 140892

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140887

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140886

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140885

llvm-svn: 140879

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140878

llvm-svn: 140870

llvm-svn: 140868

This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863

llvm-svn: 140862

Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509

llvm-svn: 140861

llvm-svn: 140855

Also take this opportunity to clean up the rounding mode pass.

llvm-svn: 140854

us to manually provide Pat<> definitions for all FP instruction patterns.

llvm-svn: 140849

llvm-svn: 140841

immediate.

llvm-svn: 140839