llvm-svn: 57553

1. Compute action in X86SelectSelect based on MVT instead of type.
2. Use TLI.getValueType(..) instead of MVT::getVT(..) because the former
   handles pointers and the later doesn't.
3. Don't pass TLI into isTypeLegal, since it already has access to it as 
   an ivar.

#2 gives fast isel some minor new functionality: handling load/stores of
pointers.

llvm-svn: 57552

llvm-svn: 57551

change the generated code, but makes the code simpler.

llvm-svn: 57550

which makes it easy to share the compare/imm folding logic with 'setcc'.
This shaves a bunch of instructions off the common select case, which
happens a lot in llvm-gcc.

llvm-svn: 57549

loading 4 into a register and then doing the compare.

llvm-svn: 57548

llvm-svn: 57547

llvm-svn: 57546

llvm-svn: 57545

llvm-svn: 57544

 - Move the EH landing-pad code and adjust it so that it works
   with FastISel as well as with SDISel.
 - Add FastISel support for @llvm.eh.exception and
   @llvm.eh.selector.

llvm-svn: 57539

SDISel typically adds them in. This makes it a little easier
to compare FastISel output with SDISel output.

llvm-svn: 57266

X86::CL that was used, emit an EXTRACT_SUBREG from the CL
super-register to CL. This more precisely describes how the
CL register is being used.

llvm-svn: 57264

getting inserted into the ValueMap. This avoids infinite
recursion in some rare cases.

llvm-svn: 56989

sequences like this:
       sete    %al
       testb   %al, %al
       jne     LBB11_1
with this:
       je      LBB11_1

llvm-svn: 56969

local register allocator's physreg liveness doesn't recognize subregs,
so it doesn't know that defs of %ecx that are immediately followed by
uses of %cl aren't dead. This comes up due to the way fast-isel emits
shift instructions.

This is a temporary workaround. Arguably, local regalloc should
handle subreg references correctly. On the other hand, perhaps
fast-isel should use INSERT_SUBREG instead of just assigning to the
most convenient super-register of %cl when lowering shifts.

This fixes MultiSource/Benchmarks/MallocBench/espresso,
MultiSource/Applications/hexxagon, and others, under -fast.

llvm-svn: 56947

This allows the 64-bit forms to use+def RSP instead of ESP. This
doesn't fix any real bugs today, but it is more precise and it
makes the debug dumps on x86-64 look more consistent.

Also, add some comments describing the CALL instructions' physreg
operand uses and defs.

llvm-svn: 56925

llvm-svn: 56829

and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.

llvm-svn: 56825

doesn't have SSE(2), with X86FastISel.

llvm-svn: 56823

llvm-svn: 56802

values for overflow.

llvm-svn: 56686

require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.

llvm-svn: 56676

require more work.

llvm-svn: 56637

load from the stub, instead of the result of the load from the stub.

llvm-svn: 56626

s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g

This sets the stage 
- to implement function notes as function attributes and 
- to distinguish between function attributes and return value attributes.

This requires corresponding changes in llvm-gcc and clang.

llvm-svn: 56622

llvm-svn: 56608

object. This will be needed to support debug info.

llvm-svn: 56508

Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.

llvm-svn: 56436

sarl    $3, %ecx

instead of:

movl    $3, %ecx
sarl    %cl, %edx

This shrinks fast isel 176.gcc by about 2000 instructions (.3%)

llvm-svn: 56413

llvm-svn: 56376

results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.

llvm-svn: 56371

catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.

llvm-svn: 56320

llvm-svn: 56311

over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.

This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.

llvm-svn: 56292

llvm-svn: 56117

If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up.  This fixes 445.gobmk on
X86-64 in fast isel.

llvm-svn: 56088

llvm-svn: 56070

to static allocas. As part of this change, refactor the
address mode code for laods and stores.

llvm-svn: 56066

Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.

llvm-svn: 55975