- Nov 02, 2010
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Chris Lattner authored
FWIW, X86 has 254 ambiguous instructions. llvm-svn: 117979
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Jim Grosbach authored
for handling the fixup necessary. llvm-svn: 117978
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Jim Grosbach authored
llvm-svn: 117977
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Bob Wilson authored
This is another part of the fix for Radar 8599955. llvm-svn: 117976
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Bob Wilson authored
llvm-svn: 117975
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Bill Wendling authored
llvm-svn: 117971
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Bill Wendling authored
llvm-svn: 117969
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Chris Lattner authored
llvm-svn: 117968
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Chris Lattner authored
llvm-svn: 117967
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- Nov 01, 2010
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Bob Wilson authored
llvm-svn: 117964
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Jakob Stoklund Olesen authored
At least X86FloatingPoint requires correct kill flags after register allocation, and targets using register scavenging benefit. Conservative kill flags are not enough. llvm-svn: 117960
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Jakob Stoklund Olesen authored
llvm-svn: 117959
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Bill Wendling authored
llvm-svn: 117956
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Bill Wendling authored
llvm-svn: 117955
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Owen Anderson authored
bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. llvm-svn: 117953
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Chris Lattner authored
from X86AsmParser.cpp llvm-svn: 117952
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Bill Wendling authored
at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. llvm-svn: 117950
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Jakob Stoklund Olesen authored
give them individual stack slots once the are actually spilled. llvm-svn: 117945
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Jakob Stoklund Olesen authored
When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
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Owen Anderson authored
llvm-svn: 117941
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Bob Wilson authored
llvm-svn: 117940
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Owen Anderson authored
llvm-svn: 117939
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Owen Anderson authored
llvm-svn: 117938
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Owen Anderson authored
llvm-svn: 117937
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Jim Grosbach authored
llvm-svn: 117936
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Owen Anderson authored
llvm-svn: 117935
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Rafael Espindola authored
llvm-svn: 117932
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Jim Grosbach authored
codegen using the patterns; the latter gates the assembler recognizing the instruction. llvm-svn: 117931
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Rafael Espindola authored
llvm-svn: 117930
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Jim Grosbach authored
llvm-svn: 117929
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Jim Grosbach authored
llvm-svn: 117927
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Rafael Espindola authored
llvm-svn: 117925
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Jim Grosbach authored
patterns as such llvm-svn: 117923
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Rafael Espindola authored
llvm-svn: 117922
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Rafael Espindola authored
llvm-svn: 117911
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Bill Wendling authored
*_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. llvm-svn: 117906
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Bill Wendling authored
peephole optimizer is disabled. That's not good at all. llvm-svn: 117905
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Bill Wendling authored
llvm-svn: 117904
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Bill Wendling authored
llvm-svn: 117903
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Chris Lattner authored
must be 8 bits. Support this memory form. llvm-svn: 117902
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