-Use the tablegen class name for the checker class name.
-Mark checker packages as hidden/not hidden.

llvm-svn: 125558

Fix 9216 - Endless loop in InstCombine pass.
The pattern "A&(A^B) -> A & ~B" recreated itself because ~B is
actually a xor -1.

llvm-svn: 125557

llvm-svn: 125552

llvm-svn: 125547

llvm-svn: 125546

llvm-svn: 125544

llvm-svn: 125543

llvm-svn: 125537

llvm-svn: 125536

llvm-svn: 125534

Simplify the spill weight calculation a bit by bypassing
getApproximateInstructionCount() and using LiveInterval::getSize() directly.
This changes the computed spill weights, but only by a constant factor in each
function. It should not affect how spill weights compare against each other, and
so it shouldn't affect code generation.

llvm-svn: 125530

Do not hoist @llvm.dbg.value. Here, @llvm.dbg.value is "referring" a value that is modified inside loop.

llvm-svn: 125529

section.

llvm-svn: 125526

The i64_buildvector test in this file relies on the alignment of i64 and
f64 types being the same, which is true for Darwin but not AAPCS.

llvm-svn: 125525

Fix PR8854. Track inserted copies to avoid read before write. Sorry, it's hard to reduce a sensible small test case.

llvm-svn: 125523

llvm-svn: 125521

for all compiler invocations.

llvm-svn: 125513

builders unhappy.

llvm-svn: 125504

llvm-svn: 125493

llvm-svn: 125490

- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489

idiom.  Change various clients to simplify their code.

llvm-svn: 125487

use in many places where we pass a pointer and size to abstract APIs
that can take C arrays, std::vector, SmallVector, etc.  It is to arrays
what StringRef is to strings.

llvm-svn: 125486

vector fp conversions.

llvm-svn: 125482

llvm-svn: 125481

llvm-svn: 125480

llvm-svn: 125477

llvm-svn: 125476

llvm-svn: 125471

have their low bits set to zero.  This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.

Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively.  Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST).  The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.

llvm-svn: 125470

llvm-svn: 125469

llvm-svn: 125466

generating i8 shift amounts for things like i1024 types.  Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h

llvm-svn: 125465

llvm-svn: 125464

llvm-svn: 125463

plus some variations of this.  According to my auto-simplifier this occurs a lot
but usually in combination with max/min idioms.  Because max/min aren't handled
yet this unfortunately doesn't have much effect in the testsuite.

llvm-svn: 125462

llvm-svn: 125460

It caused a crash in MultiSource/Benchmarks/Bullet.
Opt hit an assertion with "opt -std-compile-opts" because
Constant::getAllOnesValue doesn't know how to handle floats.

This patch added a test to reproduce the problem and a check that the
destination vector is of integer type.

Thank you Benjamin!

llvm-svn: 125459

the shift amounts are in a suitably wide type so that
we don't generate out of range constant shift amounts.

This fixes PR9028.

llvm-svn: 125458

is narrower than the shift register.  Doing an anyext provides undefined bits in
the top part of the register.

llvm-svn: 125457