The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.

<rdar://problem/10032939>

llvm-svn: 138945

An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944

Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690

llvm-svn: 138934

Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are.

llvm-svn: 138932

llvm-svn: 138931

The landingpad instruction can be removed only when its invokes are removed.

llvm-svn: 138930

Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924

This was found via a nightly build of 483.xalancbmk.

llvm-svn: 138923

llvm-svn: 138922

llvm-svn: 138918

Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912

The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches.  However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful.  Specify additional fixed bits to close those gaps.

llvm-svn: 138910

Stores sizes as uint64_t to avoid possible truncation.

llvm-svn: 138901

llvm-svn: 138898

llvm-svn: 138897

llvm-svn: 138896

llvm-svn: 138895

The landingpad instruction is required in the landing pad block. Because we're
not deleting terminating instructions, the invoke may still jump to here (see
Transforms/SCCP/2004-11-16-DeadInvoke.ll). Remove all uses of the landingpad
instruction, but keep it around until code-gen can remove the basic block.

llvm-svn: 138890

llvm-svn: 138889

llvm-svn: 138887

When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index.  This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
<rdar://problem/10046188>

llvm-svn: 138885

When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879

Fill in type legalization for MERGE_VALUES in all the various cases.  Patch by Micah Villmow.  (No testcase because the issue only showed up in an out-of-tree backend.)

llvm-svn: 138877

llvm-svn: 138874

llvm-svn: 138873

Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM.

llvm-svn: 138872

Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871

This fixes ptype.exp gdb testsuite regressions.

llvm-svn: 138869

llvm-svn: 138868

llvm-svn: 138866

Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

llvm-svn: 138864

When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862

It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

llvm-svn: 138861

llvm-svn: 138858

Make sure we don't crash when -miphoneos-version-min is specified on x86.  Hopefully this will fix gcc testsuite failures.

llvm-svn: 138856

Patch by Sanjoy Das

llvm-svn: 138853

- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851

llvm-svn: 138850

whenever AVX is enabled.

llvm-svn: 138849

llvm-svn: 138848