Commits · e44dea9f6ba6279c5daf070c39386b7f3407384a · Roger Ferrer / llvm-epi-0.8 · GitLab

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Dec 18, 2017
- Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC. · e44dea9f
  Dimitry Andric authored Dec 18, 2017
  e44dea9f
- [Hexagon] Higher versions of HVX imply presence of lower versions · eba8c0c6
  Krzysztof Parzyszek authored Dec 18, 2017
  eba8c0c6
- [IR] Support the new TBAA metadata format in IR verifier · 422a380a
  Ivan A. Kosarev authored Dec 18, 2017
  422a380a
- Fix inconsistent line endings in ARCDisassembler.cpp. NFC. · ca5b0f3f
  Dimitry Andric authored Dec 18, 2017
  ca5b0f3f
- i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004 · 72592637
  Krzysztof Parzyszek authored Dec 18, 2017
  72592637
- [Hexagon] Generate HVX code for vector sign-, zero- and any-extends · 6b589e59
  Krzysztof Parzyszek authored Dec 18, 2017
  6b589e59
- [X86] Regenerate test to improve codegen testing for D41350 · f947137e
  Simon Pilgrim authored Dec 18, 2017
  f947137e
- [Hexagon] Prefer to widen HVX vectors instead of promoting · 5439a70d
  Krzysztof Parzyszek authored Dec 18, 2017
  5439a70d
- Removed unused DominanceFrontier · d89d0b64
  Matt Arsenault authored Dec 18, 2017
  d89d0b64
- [ThinLTO] Make distributed indexes test more robust · 9ecaaff2
  Teresa Johnson authored Dec 18, 2017
  9ecaaff2
- [PGO] add MST min edge selection heuristic to ensure non-zero entry count · 19fb5b46
  Xinliang David Li authored Dec 18, 2017
  19fb5b46
- [YAML] Add support for non-printable characters · b213b27e
  Francis Visoiu Mistrih authored Dec 18, 2017
  b213b27e
- [IR] Add MDBuilder helpers for the new TBAA metadata format · 04e1d017
  Ivan A. Kosarev authored Dec 18, 2017
  04e1d017
- [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified · 09f56a54
  Sander de Smalen authored Dec 18, 2017
  09f56a54
- Reland "[mips] Fix the target specific instruction verifier" · fd8c65e8
  Simon Dardis authored Dec 18, 2017
  fd8c65e8
- [Memcpy Loop Lowering] Remove the fixed int8 lowering. · 5fb624a3
  Sean Fertile authored Dec 18, 2017
  5fb624a3
- [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction · 19097918
  Sander de Smalen authored Dec 18, 2017
  19097918
- [LVI] Support for ashr in LVI · 1acab002
  Max Kazantsev authored Dec 18, 2017
  1acab002
- [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524 · 8ee540c0
  Diana Picus authored Dec 18, 2017
  8ee540c0
- Constexprify LaneBitmask factory methods. · bc8fdaaf
  Benjamin Kramer authored Dec 18, 2017
  bc8fdaaf
- [ConstantRange] Support for ashr in ConstantRange computation · d792171e
  Max Kazantsev authored Dec 18, 2017
  d792171e
- Revert "[mips] Fix the target specific instruction verifier" · f70af977
  Simon Dardis authored Dec 18, 2017
  f70af977
- [mips] Fix the target specific instruction verifier · c3c0d459
  Simon Dardis authored Dec 18, 2017
  c3c0d459
- [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors) · fce0c1c4
  Sander de Smalen authored Dec 18, 2017
  fce0c1c4
- [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support · ce1e0975
  Sander de Smalen authored Dec 18, 2017
  ce1e0975
- [ThinLTO] Remove unused code · c95b4960
  Eugene Leviant authored Dec 18, 2017
  c95b4960
- AArch64: work around how Cyclone handles "movi.2d vD, #0". · 9097a07e
  Tim Northover authored Dec 18, 2017
  9097a07e
- [TargetLibraryInfo] Discard library functions with incorrectly sized integers · 7bd3fb15
  Igor Laevsky authored Dec 18, 2017
  7bd3fb15
- [ARM] Adjust test checks · fd967f2f
  Sam Parker authored Dec 18, 2017
  fd967f2f
- [DAGCombine] Move AND nodes to multiple load leaves · 00804efd
  Sam Parker authored Dec 18, 2017
  00804efd
- [NFC][CodeGen][ExpandMemCmp] Fix documentation. · 6f42de30
  Clement Courbet authored Dec 18, 2017
  6f42de30
- [X86] Use mattr instead of mcpu in some of the cost model tests. · 7034d401
  Craig Topper authored Dec 18, 2017
  7034d401
- [SROA] Disable non-whole-alloca splits by default · c6faf154
  Hiroshi Inoue authored Dec 18, 2017
  c6faf154
- [X86] Fix mistake that I made when splitting up the setOperationAction calls recently. · 8e2837cc
  Craig Topper authored Dec 18, 2017
  8e2837cc
- [CGP] Fix the handling select inst in complex addressing mode · b0b67a8d
  Serguei Katkov authored Dec 18, 2017
  b0b67a8d
- [x86] add tests for finite libcall lowering (PR35672); NFC · 9da049fa
  Sanjay Patel authored Dec 18, 2017
  9da049fa
Dec 17, 2017
- Re-commit "Properly handle multi-element and dynamically sized allocas in... · 3603de2f
  Bjorn Steinbrink authored Dec 17, 2017
  3603de2f
- [X86] Add test cases that show cases where buildvector of extract and inserts... · 255a76d6
  Craig Topper authored Dec 17, 2017
  255a76d6
- [X86] Make the code that creates fmaddsub from build_vector of extracts and... · fd8d0408
  Craig Topper authored Dec 17, 2017
  fd8d0408
- [X86] Regenerate truncated rotation tests + add missing 32-bit checks · 406d04a9
  Simon Pilgrim authored Dec 17, 2017
  406d04a9