or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976

llvm-svn: 132964

we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882

functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.

llvm-svn: 132880

memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.

llvm-svn: 132869

rdar://9431466

llvm-svn: 132864

PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.

llvm-svn: 132826

Chris fixed this README a while back by changing how clang generates code for structs like the given struct.

llvm-svn: 132815

llvm-svn: 132795

Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.

llvm-svn: 132789

The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781

No functional change.

Part of PR6965

llvm-svn: 132763

load.  rdar://problem/6373334

llvm-svn: 132696

rdar://problem/5993888

llvm-svn: 132606

Part of rdar://9119939

llvm-svn: 132510

allocation orders.

llvm-svn: 132509

llvm-svn: 132479

rdar://problem/6373334

llvm-svn: 132458

No functional change.

llvm-svn: 132455

llvm-svn: 132451

llvm-svn: 132424

llvm-svn: 132419

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398

patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388

directives.

Fixes PR9826.

llvm-svn: 132317

same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314

subregisters of the 64 bit ones.

llvm-svn: 132313

llvm-svn: 132238

llvm-svn: 132230

was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

llvm-svn: 132225

The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.

llvm-svn: 132199

refer to them.

I tested this with both check-all and the gdb testsuite.

llvm-svn: 132187

crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].

llvm-svn: 132163

llvm-svn: 132108

rdar://problem/6920088

llvm-svn: 132105

Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.

The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099

llvm-svn: 132062

MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.

llvm-svn: 132057

LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

llvm-svn: 132033