llvm-svn: 59074

llvm-svn: 59016

llvm-svn: 59006

llvm-svn: 58949

and breaks llvm-gcc

llvm-svn: 58926

FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?

llvm-svn: 58917

llvm-svn: 58899

llvm-svn: 58897

llvm-svn: 58896

llvm-svn: 58893

llvm-svn: 58883

llvm-svn: 58882

llvm-svn: 58877

llvm-svn: 58872

llvm-svn: 58869

This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.

llvm-svn: 58859

llvm-svn: 58836

llvm-svn: 58828

llvm-svn: 58818

- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808

llvm-svn: 58800

llvm-svn: 58793

llvm-svn: 58790

llvm-svn: 58789

llvm-svn: 58780

Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.

llvm-svn: 58764

priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748

llvm-svn: 58725

llvm-svn: 58714

llvm-svn: 58708

llvm-svn: 58707

For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.

This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.

llvm-svn: 58688

llvm-svn: 58683

llvm-svn: 58671

llvm-svn: 58644

llvm-svn: 58643

Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.

llvm-svn: 58626

adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624

llvm-svn: 58533

llvm-svn: 58532