For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569

The difference between isPseudo and isCodeGenOnly is a bit murky, but
isCodeGenOnly should eventually go away.  It is used for instructions
that are clones of real instructions with slightly different properties.

The standard pseudo-instructions never mirror real instructions, so they
are definitely in the isPseudo category.

llvm-svn: 141567

compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic

llvm-svn: 141564

llvm-svn: 141563

The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562

hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560

llvm-svn: 141557

isel doesn't ignore it.

llvm-svn: 141548

llvm-svn: 141535

llvm-svn: 141534

llvm-svn: 141533

ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529

llvm-svn: 141527

the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

llvm-svn: 141523

llvm-svn: 141508

llvm-svn: 141505

A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

llvm-svn: 141500

In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499

llvm-svn: 141498

llvm-svn: 141495

llvm-svn: 141492

llvm-svn: 141490

llvm-svn: 141485

llvm-svn: 141484

llvm-svn: 141483

llvm-svn: 141481

llvm-svn: 141476

llvm-svn: 141475

llvm-svn: 141474

conversion instructions. 

llvm-svn: 141473

llvm-svn: 141472

instruction selector to generate them.

llvm-svn: 141471

llvm-svn: 141470

across unwind edges. This is for the back-end which expects such things.

The code is from the original SjLj EH pass.

llvm-svn: 141463

cross build, so that a native version of clang-tblgen is available.
Should unbreak Clang cross build.

Also disable Polly for the native tool build, since it depends on
external libraries which may not be available, and it isn't required
anyway.

llvm-svn: 141454

llvm-svn: 141451

llvm-svn: 141450

llvm-svn: 141449

llvm-svn: 141448

llvm-svn: 141447