Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.

llvm-svn: 27201

llvm-svn: 27166

llvm-svn: 27148

llvm-svn: 27132

llvm-svn: 27100

llvm-svn: 27073

llvm-svn: 27070

llvm-svn: 26911

llvm-svn: 26895

llvm-svn: 26891

llvm-svn: 26789

llvm-svn: 26649

llvm-svn: 26640

llvm-svn: 26479

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

llvm-svn: 26250

llvm-svn: 26249

'fpimm' in .td files is now TargetConstantFP.

llvm-svn: 25771

llvm-svn: 25312

Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222

hasInFlag, hasOutFlag.

llvm-svn: 25155

llvm-svn: 25107

inserted in the code.

llvm-svn: 25104

llvm-svn: 25096

llvm-svn: 25058

llvm-svn: 25005

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997

llvm-svn: 24989

llvm-svn: 24934

llvm-svn: 24901

llvm-svn: 24879

llvm-svn: 24870

llvm-svn: 24819

one for use with extload, one for use with sextload and zextload, which
are integer only.

llvm-svn: 24814

llvm-svn: 24787

llvm-svn: 24748

* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726

llvm-svn: 24723

llvm-svn: 24715

OtherVT, it cannot be compare to type of 1st operand which is an integer type.

llvm-svn: 24713