llvm-svn: 163561

llvm-svn: 163557

llvm-svn: 163556

and InlineAsmVariant don't match.

llvm-svn: 163550

llvm-svn: 163547

llvm-svn: 163545

and update the printOperand() function accordingly.

llvm-svn: 163544

llvm-svn: 163542

llvm-svn: 163539

The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.

Don't do that if the sub is predicated - the flags are not written
unconditionally.

<rdar://problem/12263428>

llvm-svn: 163535

llvm-svn: 163532

llvm-svn: 163530

    
- Fix an remaining issue of PR11674 as well

llvm-svn: 163528

  Improve AQ instruction selection in the Hexagon MI scheduler.

llvm-svn: 163523

This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs).

llvm-svn: 163519

llvm-svn: 163518

- If a boolean value is generated from CMOV and tested as boolean value,
  simplify the use of test result by referencing the original condition.
  RDRAND intrinisc is one of such cases.

llvm-svn: 163516

Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types.

llvm-svn: 163511

llvm-svn: 163510

llvm-svn: 163509

Stack Coloring: When searching for disjoint regions, do not compare intervals twice or to theirself.

llvm-svn: 163508

llvm-svn: 163507

The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer.
I've added the "zeroinitializer" case in this patch.

llvm-svn: 163506

llvm-svn: 163504

llvm-svn: 163503

- The C API should be stable
- InlineAsm::AsmDialect is not exposed to C
- The function didn't match the prototype so this was unreachable code

llvm-svn: 163502

llvm-svn: 163496

llvm-svn: 163495

llvm-svn: 163494

llvm-svn: 163491

llvm-svn: 163485

llvm-svn: 163484

llvm-svn: 163483

llvm-svn: 163480

LiveVariables: Compute a set of defs and kills to speed up updating LV during critical edge splitting.

Previously we checked if the register is def'd in a block via the def/use list a
nd walked the list of kills to check if the register is killed in a block. Both
of these checks can be made much cheaper by walking the block first and
recording all defs and kills.

This reduces the compile time of the test case from PR13651 from 40s to 15s at
-O2. The compile time is still dominated by LV updating but now the main culprit
is SparseBitVector's slowness.

llvm-svn: 163478

llvm-svn: 163473

llvm-svn: 163463

llvm-svn: 163461

Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct.

llvm-svn: 163458

llvm-svn: 163454