llvm-svn: 30844

a framework for doing it right.  This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.

Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.

llvm-svn: 30817

llvm-svn: 30815

llvm-svn: 30814

llvm-svn: 30813

llvm-svn: 30812

llvm-svn: 30811

Fix a bug where the asmstring for PSUBQrm was wrong.

llvm-svn: 30810

llvm-svn: 30809

llvm-svn: 30808

  PDI_binop_rm -> PDI_binop_rm_int
  PDI_binop_rmi -> PDI_binop_rmi_int

to make it clear that these are for use with intrinsics.

llvm-svn: 30807

llvm-svn: 30806

llvm-svn: 30805

This allows us to use the multiclass for other packs.

llvm-svn: 30804

llvm-svn: 30800

llvm-svn: 30797

llvm-svn: 30796

llvm-svn: 30795

llvm-svn: 30794

llvm-svn: 30793

llvm-svn: 30792

llvm-svn: 30791

llvm-svn: 30790

llvm-svn: 30789

llvm-svn: 30788

llvm-svn: 30787

llvm-svn: 30786

llvm-svn: 30785

Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].

llvm-svn: 30784

llvm-svn: 30783

llvm-svn: 30694

operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241

llvm-svn: 30112

llvm-svn: 29275

(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042

llvm-svn: 28984

llvm-svn: 28979

llvm-svn: 28864

llvm-svn: 28862

llvm-svn: 28860