llvm-svn: 37746

llvm-svn: 37743

llvm-svn: 37740

Properly handle kills of a physical register which has sub-registers that are read by later instructions.

llvm-svn: 37739

llvm-svn: 37725

and code quality by ~2% on my tests.

A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.

llvm-svn: 37724

extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704

llvm-svn: 37703

std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.

llvm-svn: 37701

llvm-svn: 37688

TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.

llvm-svn: 37687

(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))

llvm-svn: 37685

Avoid if-converting simple block that ends with unconditional branch or fallthrough unless it branches / falls to the 'false' block. Not profitable, may end up increasing code size.

llvm-svn: 37660

for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.

llvm-svn: 37656

llvm-svn: 37651

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37643

llvm-svn: 37640

llvm-svn: 37634

llvm-svn: 37633

by making it non-recursive

llvm-svn: 37629

llvm-svn: 37626

llvm-svn: 37623

1. Consider all possible ifcvt cases at once. No longer restricted to bottom
   up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
   ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.

llvm-svn: 37613

llvm-svn: 37608

llvm-svn: 37607

for tied register constraints.

llvm-svn: 37601

llvm-svn: 37599

llvm-svn: 37597

llvm-svn: 37593

llvm-svn: 37590

llvm-svn: 37581

If BB is predicated, invalidate its predecessor(s) which would if-convert it. It needs to be re-analyzed.

llvm-svn: 37580

llvm-svn: 37579

llvm-svn: 37577

implementation for x86.

llvm-svn: 37576

llvm-svn: 37575

turned on.  Likewise for scanning of invokes to mark landing pads.

llvm-svn: 37570

VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.

This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.

llvm-svn: 37569