.bc file if they are supposed to be implicit.  This is cool, except that it
checked *after* constant expr folding: improving constant expr folding could
cause the .bc reader to assert out on old .bc files.  Move the check so that
it checks all simple constants, but no constantexprs.

llvm-svn: 27480

llvm-svn: 27479

llvm-svn: 27478

Instruction::InsertElement.

llvm-svn: 27477

Also MOVPDI2DIrr.

llvm-svn: 27476

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27473

2. A shuffle mask element can also be an undef.

llvm-svn: 27472

llvm-svn: 27471

llvm-svn: 27470

llvm-svn: 27469

This reduces Core size, yay.

llvm-svn: 27468

Convert vsldoi(x,x) to work the same way other (x,x) cases work.

llvm-svn: 27467

llvm-svn: 27463

llvm-svn: 27460

llvm-svn: 27457

llvm-svn: 27453

us to compile oh-so-realistic stuff like this:

 vec_vperm(A, B, (vector unsigned char){14});

to:
        vspltb v0, v0, 14

instead of:

        vspltisb v0, 14
        vperm v0, v2, v1, v0

llvm-svn: 27452

lower it and LLVM to have one fewer intrinsic.  This implements
CodeGen/PowerPC/vec_shuffle.ll

llvm-svn: 27450

vperm with a perm mask lvx'd from the constant pool.

llvm-svn: 27448

llvm-svn: 27446

llvm-svn: 27445

llvm-svn: 27444

llvm-svn: 27442

llvm-svn: 27440

llvm-svn: 27439

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

CodeGen/X86/2006-04-04-CrossBlockCrash.ll

llvm-svn: 27436

llvm-svn: 27434

llvm-svn: 27433

or custom lowering fails.

llvm-svn: 27432

llvm-svn: 27428

llvm-svn: 27427

llvm-svn: 27425

llvm-svn: 27423

llvm-svn: 27421

llvm-svn: 27419

llvm-svn: 27418

llvm-svn: 27417

llvm-svn: 27416