llvm-svn: 135154

llvm-svn: 135151

instructions.

llvm-svn: 135146

Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector.

llvm-svn: 135145

[VECTOR-SELECT]
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.

llvm-svn: 135144

llvm-svn: 135143

llvm-svn: 135142

Part of rdar://9761830

llvm-svn: 135133

llvm-svn: 135132

TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.

This patch is but one small step towards fixing this. 500 more steps to go. :-(

llvm-svn: 135131

Original commit message:

Count references to interference cache entries.

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135130

llvm-svn: 135127

Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.

llvm-svn: 135126

llvm-svn: 135124

Fixes rdar://9761830

llvm-svn: 135123

llvm-svn: 135122

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135121

Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.

llvm-svn: 135120

llvm-svn: 135119

llvm-svn: 135118

llvm-svn: 135117

Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116

The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.

The correct fix here is to use reference counts on the cache entries.
Coming up.

llvm-svn: 135113

llvm-svn: 135112

llvm-svn: 135111

llvm-svn: 135110

Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109

llvm-svn: 135107

Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode.  Switch ARM over to using that rather than its own special MCInstrDesc bits.

llvm-svn: 135106

The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

llvm-svn: 135103

Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102

llvm-svn: 135099

llvm-svn: 135098

Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

llvm-svn: 135097

llvm-svn: 135096

llvm-svn: 135095

llvm-svn: 135094

llvm-svn: 135093

llvm-svn: 135092

general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088