llvm-svn: 136319

This takes the new 'resume' instruction and turns it into a direct jump to the
caller's landing pad code. The caller's landingpad instruction is merged with
the landingpad instructions of the callee. This is a bit rough and makes some
assumptions in how the code works. But it passes a simple test.

llvm-svn: 136313

UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

llvm-svn: 136312

If true and 'model' parameter is not an absolute path, a temp directory will be prepended.
Make it true by default to match current behaviour.

llvm-svn: 136310

Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.

llvm-svn: 136295

This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292

llvm-svn: 136289

llvm-svn: 136288

llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287

llvm-svn: 136286

Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285

llvm-svn: 136284

llvm-svn: 136283

llvm-svn: 136282

llvm-svn: 136281

llvm-svn: 136280

llvm-svn: 136279

llvm-svn: 136278

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277

llvm-svn: 136275

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274

llvm-svn: 136272

llvm-svn: 136269

llvm-svn: 136267

llvm-svn: 136266

Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264

llvm-svn: 136263

llvm-svn: 136261

llvm-svn: 136260

llvm-svn: 136259

Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions.  Temporarily XFAIL the asm parsing tests for these instructions.

llvm-svn: 136255

This adds the new instructions 'landingpad' and 'resume'.

llvm-svn: 136253

Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252

llvm-svn: 136250

X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics.

llvm-svn: 136249

The numbering of LLVMOpcode is supposed to be stable; revert my earlier change, and append Fence onto the end.

llvm-svn: 136245

llvm-svn: 136244

Add a generic 'capacity_in_bytes' function to allow inspection of memory usage of various data structures.

llvm-svn: 136233

llvm-svn: 136229

llvm-svn: 136228