miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.

llvm-svn: 27933

llvm-svn: 27930

llvm-gcc4 boostrap.  Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).

llvm-svn: 27922

llvm-svn: 27899

llvm-svn: 27893

DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.

llvm-svn: 27874

llvm-svn: 27863

llvm-svn: 27846

the code in GCC PR26546.

llvm-svn: 27780

llvm-svn: 27775

and a shuffle.  For this:

void %test2(<4 x float>* %F, float %f) {
        %tmp = load <4 x float>* %F             ; <<4 x float>> [#uses=2]
        %tmp3 = add <4 x float> %tmp, %tmp              ; <<4 x float>> [#uses=1]
        %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2               ; <<4 x float>> [#uses=2]
        %tmp6 = add <4 x float> %tmp2, %tmp2            ; <<4 x float>> [#uses=1]
        store <4 x float> %tmp6, <4 x float>* %F
        ret void
}

we now get this on X86 (which will get better):

_test2:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, %xmm1
        shufps $3, %xmm1, %xmm1
        movaps %xmm0, %xmm2
        shufps $1, %xmm2, %xmm2
        unpcklps %xmm1, %xmm2
        movss 8(%esp), %xmm1
        unpcklps %xmm1, %xmm0
        unpcklps %xmm2, %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        ret

instead of:

_test2:
        subl $28, %esp
        movl 32(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%esp)
        movss 36(%esp), %xmm0
        movss %xmm0, 8(%esp)
        movaps (%esp), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        addl $28, %esp
        ret

llvm-svn: 27765

to write one pattern for vector stores instead of 4.

llvm-svn: 27730

buildvectors.

llvm-svn: 27723

llvm-svn: 27695

about "dereferencing type-punned pointer will break strict-aliasing rules"

llvm-svn: 27671

llvm-svn: 27632

llvm-svn: 27606

Implement support for the formal_arguments node.  To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload

llvm-svn: 27604

getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll

llvm-svn: 27602

llvm-svn: 27586

llvm-svn: 27580

llvm-svn: 27578

llvm-svn: 27574

llvm-svn: 27559

llvm-svn: 27542

to match again :)

llvm-svn: 27533

llvm-svn: 27529

as its input.

llvm-svn: 27528

  store vector to $esp
  store element to $esp + sizeof(VT) * index
  load  vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!

llvm-svn: 27517

llvm-svn: 27514

section.

llvm-svn: 27503

entry point of a function.

llvm-svn: 27494

llvm-svn: 27491

2. A shuffle mask element can also be an undef.

llvm-svn: 27472

CodeGen/X86/2006-04-04-CrossBlockCrash.ll

llvm-svn: 27436

or custom lowering fails.

llvm-svn: 27432

legal.

llvm-svn: 27402

  promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
  to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.

llvm-svn: 27399

llvm-svn: 27391

llvm-svn: 27380