is morphed by AnalyzeNewNode into a previously
processed node, and different result values of
that node are remapped to values with different
nodes, then we could end up using wrong values
here [we were assuming that all results remap
to values with the same underlying node].  This
seems theoretically possible, but I don't have
a testcase.  The meat of the patch is in the
changes to AnalyzeNewNode/AnalyzeNewValue and
ReplaceNodeWith.  While there, I changed names
like RemapNode to RemapValue, since it really
remaps values.  To tell the truth, I would be
much happier if we were only remapping nodes
(it would simplify a bunch of logic, and allow
for some cute speedups) but I haven't yet worked
out how to do that.

llvm-svn: 58372

llvm-svn: 58371

llvm-svn: 58370

- Create and update spill slot live intervals.
- Lots of bug fixes.

llvm-svn: 58367

 - No functionality change.

llvm-svn: 58355

 - No functionality change.

llvm-svn: 58352

llvm-svn: 58351

EnableFastISelAbort variables for Release mode instead of
using ifdefs in the code.

llvm-svn: 58350

 - One functionality change, '\\' in a name is now printed as a hex
   escape instead of "\\\\". This is consistent with other users of
   PrintEscapedString.

llvm-svn: 58343

llvm-svn: 58340

Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.

llvm-svn: 58338

ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG.  This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes.  Probably PPC should
simply custom lower the original conversion.

llvm-svn: 58329

id could end up being wrong mostly because of
forgetting to remap new nodes that morphed into
processed nodes through CSE.

llvm-svn: 58323

llvm-svn: 58320

llvm-svn: 58319

a memset using 16-byte XMM stores, but where the stack realignment code
didn't work.  Until it does (PR2962) disable use of xmm regs in memcpy
and memset formation for linux and other targets with insufficiently
aligned stacks.

This is part of PR2888

llvm-svn: 58317

llvm-svn: 58314

llvm-svn: 58312

Avoid putting a split past the end of the live range; always shrink wrap live interval in the barrier mbb.

llvm-svn: 58309

llvm-svn: 58297

Re-apply 55137 with fixes.

llvm-svn: 58296

llvm-svn: 58294

llvm-svn: 58290

Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278

Add setSubgraphColor to color an entire portion of a SelectionDAG.  This
will be used to support debug features in TableGen.

llvm-svn: 58257

Fix PR2634.  Create new virtual registers from spills early so that we
can give it the same stack slot as the spilled interval if it is folded.
This prevents the fold/unfold code from pointing to the wrong register.

llvm-svn: 58255

(and a bunch of other node types).  While there, I
added a doNotCSE predicate and used it to reduce code
duplication (some of the duplicated code was wrong...).
This fixes ARM/cse-libcalls.ll when using LegalizeTypes. 

llvm-svn: 58249

worklist twice: UpdateNodeOperands could morph
a new node into a node already on the worklist.
We would then recalculate the NodeId for this
existing node and add it to the worklist.  The
testcase is ARM/cse-libcalls.ll, the problem
showing up once UpdateNodeOperands is taught to
do CSE for calls.

llvm-svn: 58246

If it is not part of a loop it is obviously invariant wrt to all loops.

llvm-svn: 58240

that need it to require it by ID.

llvm-svn: 58238

codegen infrastructure, by default.  Please report
any breakage to the mailing lists.

llvm-svn: 58232

llvm-svn: 58231

For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.

llvm-svn: 58230

LargeBlockInfo, we can now dramatically simplify their implementation
and speed them up at the same time.  Now the code has time proportional
to the number of uses of the alloca, not the size of the block.

This also eliminates code that tried to batch up different allocas which
are used in the same blocks, and eliminates the 'retry list' logic which
was baroque and no unneccesary.  In addition to being a speedup for crazy
cases, this is also a nice cleanup:

PromoteMemoryToRegister.cpp |  270 +++++++++++++++-----------------------------
 1 file changed, 96 insertions(+), 174 deletions(-)

llvm-svn: 58229

a trivial dense map.  Use this in RewriteSingleStoreAlloca to
avoid aggressively rescanning blocks over and over again.  This
fixes PR2925, speeding up mem2reg on the testcase in that bug
from 4.56s to 0.02s in a debug build on my machine.

llvm-svn: 58227

150, based on llvm-test measurements.

llvm-svn: 58225

Thanks to Török Edwin for the awesome reduced testcase.

llvm-svn: 58199

Do not shrink wrap live interval in a mbb if it's livein any of its successor blocks. The mbb can be revisited again after all of the successors are processed.

llvm-svn: 58184

Patch by Frits van Bommel!

llvm-svn: 58175

llvm-svn: 58174