We verify that the LiveInterval is live at uses and defs, and that all
instructions have a SlotIndex.

Stuff we don't check yet:

- Is the LiveInterval minimal?
- Do all defs correspond to instructions or phis?
- Do all defs dominate all their live ranges?
- Are all live ranges continually reachable from their def?

llvm-svn: 110386

be killed before being redefined.

These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.

llvm-svn: 110362

we sometimes compare singular iterators, reported by ENABLE_EXPENSIVE_CHECKS.
This fixes PR7825.

llvm-svn: 110355

because it could create such things. This fixes a MingW buildbot test failure.

llvm-svn: 110279

This helps avoid silly code:

    %R0<def = LOAD <fi#5>
    STORE <fi#5>, %R0<kill>

llvm-svn: 110266

We are now at a point where we can split around simple single-entry, single-exit
loops, although still with some bugs.

llvm-svn: 110257

llvm-svn: 110255

llvm-svn: 110248

llvm-svn: 110244

be triggered by valid, if dubious, IR.

llvm-svn: 110240

While spilling live registers at the end of block check whether they are used by DBG_VALUE machine instructions or not. If a spilled register is used by DBG_VALUE machine instruction then insert a new DBG_VALUE machine instruction to encode variable's new location on stack.

llvm-svn: 110235

llvm-svn: 110234

llvm-svn: 110183

When the normalizeSpillWeights function was introduced, I forgot to remove this
normalization.

This change could affect register allocation. Hopefully for the better.

llvm-svn: 110119

llvm-svn: 110069

llvm-svn: 110045

Fixes potential ambiguity problems on VS 2010.

Patch by nobled!

llvm-svn: 110029

ISD::AND case of TargetLowering::SimplifyDemandedBits.

llvm-svn: 110019

llvm-svn: 109966

check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.

llvm-svn: 109854

Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ownership of the TargetAsmBackend and the MCCodeEmitter.

llvm-svn: 109767

llvm-svn: 109765

multiple defs, like t2LDRSB_POST.

The first def could accidentally steal the physreg that the second, tied def was
required to be allocated to.

Now, the tied use-def is treated more like an early clobber, and the physreg is
reserved before allocating the other defs.

This would never be a problem when the tied def was the only def which is the
usual case.

This fixes MallocBench/gs for thumb2 -O0.

llvm-svn: 109715

llvm-svn: 109608

llvm-svn: 109538

llvm-svn: 109525

recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.

llvm-svn: 109519

llvm-svn: 109513

llvm-svn: 109511

protectors, to be near the stack protectors on the stack. Accomplish this by
tagging the stack object with a predicate that indicates that it would trigger
this. In the prolog-epilog inserter, assign these objects to the stack after the
stack protector but before the other objects.

llvm-svn: 109481

rewrite instructions for live range splitting.

Still work in progress.

llvm-svn: 109469

llvm-svn: 109468

llvm-svn: 109462

The "excess register pressure" returned by HighRegPressure() is not accurate enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling.

llvm-svn: 109449

llvm-svn: 109415

llvm-svn: 109402

may be used uninitialized in the callers of HighRegPressure.

llvm-svn: 109393

llvm-svn: 109388

llvm-svn: 109383

those.  Radar 8231572.

llvm-svn: 109367